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Clean up vecgtored interrupts

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This commit is contained in:
David Harris 2022-12-20 16:53:09 -08:00
parent dd0a02f0c8
commit 5d91b3044f
1 changed files with 17 additions and 16 deletions
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33
pipelined/src/privileged/csr.sv
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@ -97,12 +97,13 @@ module csr #(parameter
logic IllegalCSRMWriteReadonlyM; logic IllegalCSRMWriteReadonlyM;
logic [`XLEN-1:0] CSRReadVal2M; logic [`XLEN-1:0] CSRReadVal2M;
logic [11:0] MIP_REGW_writeable; logic [11:0] MIP_REGW_writeable;
logic [`XLEN-1:0] TVec, TrapVector, NextFaultMtvalM; logic [`XLEN-1:0] TVecM, TrapVectorM, NextFaultMtvalM;
logic MTrapM, STrapM; logic MTrapM, STrapM;
logic [`XLEN-1:0] EPC; logic [`XLEN-1:0] EPC;
logic RetM; logic RetM;
logic SelMtvec; logic SelMtvecM;
logic [`XLEN-1:0] TVecAlignedM;
logic InstrValidNotFlushedM; logic InstrValidNotFlushedM;
assign InstrValidNotFlushedM = ~StallW & ~FlushW; assign InstrValidNotFlushedM = ~StallW & ~FlushW;
@ -129,30 +130,30 @@ module csr #(parameter
// > Allowing coarser alignments in Vectored mode enables vectoring to be // > Allowing coarser alignments in Vectored mode enables vectoring to be
// > implemented without a hardware adder circuit. // > implemented without a hardware adder circuit.
// For example, we could require m/stvec be aligned on 7 bits to let us replace the adder directly below with // For example, we could require m/stvec be aligned on 7 bits to let us replace the adder directly below with
// [untested] TrapVector = {TVec[`XLEN-1:7], CauseM[3:0], 4'b0000} // [untested] TrapVectorM = {TVec[`XLEN-1:7], CauseM[3:0], 4'b0000}
// However, this is program dependent, so not implemented at this time. // However, this is program dependent, so not implemented at this time.
assign SelMtvec = (NextPrivilegeModeM == `M_MODE); // Select trap vector from STVEC or MTVEC and word-align
mux2 #(`XLEN) tvecmux(STVEC_REGW, MTVEC_REGW, SelMtvec, TVec); assign SelMtvecM = (NextPrivilegeModeM == `M_MODE);
mux2 #(`XLEN) tvecmux(STVEC_REGW, MTVEC_REGW, SelMtvecM, TVecM);
assign TVecAlignedM = {TVecM[`XLEN-1:2], 2'b00};
// Support vectored interrupts
if(`VECTORED_INTERRUPTS_SUPPORTED) begin:vec if(`VECTORED_INTERRUPTS_SUPPORTED) begin:vec
always_comb logic VectoredM;
if (TVec[1:0] == 2'b01 & InterruptM) logic [`XLEN-1:0] TVecPlusCauseM;
TrapVector = {TVec[`XLEN-1:2] + {{(`XLEN-2-`LOG_XLEN){1'b0}}, CauseM}, 2'b00}; assign VectoredM = InterruptM & (TVecM[1:0] == 2'b01);
else assign TVecPlusCauseM = TVecAlignedM + {{(`XLEN-2-`LOG_XLEN){1'b0}}, CauseM, 2'b00};
TrapVector = {TVec[`XLEN-1:2], 2'b00}; mux2 #(`XLEN) trapvecmux(TVecAlignedM, TVecPlusCauseM, VectoredM, TrapVectorM);
end end else
else begin assign TrapVectorM = TVecAlignedM;
assign TrapVector = {TVec[`XLEN-1:2], 2'b00};
end
// Trap Returns // Trap Returns
// A trap sets the PC to TrapVector // A trap sets the PC to TrapVector
// A return sets the PC to MEPC or SEPC // A return sets the PC to MEPC or SEPC
assign RetM = mretM | sretM; assign RetM = mretM | sretM;
mux2 #(`XLEN) epcmux(SEPC_REGW, MEPC_REGW, mretM, EPC); mux2 #(`XLEN) epcmux(SEPC_REGW, MEPC_REGW, mretM, EPC);
mux3 #(`XLEN) pcmux3(PCNext2F, EPC, TrapVector, {TrapM, RetM}, UnalignedPCNextF); mux3 #(`XLEN) pcmux3(PCNext2F, EPC, TrapVectorM, {TrapM, RetM}, UnalignedPCNextF);
/////////////////////////////////////////// ///////////////////////////////////////////
// CSRWriteValM // CSRWriteValM