forked from Github_Repos/cvw
radix-4 divider passing tests
This commit is contained in:
Katherine Parry
parent
254ebf478e
commit
5d5f79eb8f
1048
pipelined/srt/qsel4.sv
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1048
pipelined/srt/qsel4.sv
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File diff suppressed because it is too large
Load Diff
2
pipelined/srt/sim-srt4
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2
pipelined/srt/sim-srt4
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@ -0,0 +1,2 @@
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vsim -do "do srt-radix4.do"
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1
pipelined/srt/sim-srt4-batch
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1
pipelined/srt/sim-srt4-batch
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vsim -c -do "do srt-radix4.do"
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31
pipelined/srt/srt-radix4.do
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pipelined/srt/srt-radix4.do
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# srt.do
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#
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# David_Harris@hmc.edu 19 October 2021
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# Use this wally-pipelined.do file to run this example.
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# Either bring up ModelSim and type the following at the "ModelSim>" prompt:
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# do wally-pipelined.do
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# or, to run from a shell, type the following at the shell prompt:
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# vsim -do wally-pipelined.do -c
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# (omit the "-c" to see the GUI while running from the shell)
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onbreak {resume}
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# create library
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if [file exists work] {
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vdel -all
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}
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vlib work
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vlog +incdir+../config/rv64gc +incdir+../config/shared srt-radix4.sv testbench-radix4.sv qsel4.sv ../src/generic/flop/flop*.sv ../src/generic/mux.sv ../src/generic/lzc.sv
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vopt +acc work.testbenchradix4 -o workopt
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vsim workopt
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-- display input and output signals as hexidecimal values
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add wave /testbenchradix4/*
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add wave /testbenchradix4/srtradix4/*
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add wave /testbenchradix4/srtradix4/qsel4/*
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add wave /testbenchradix4/srtradix4/otfc4/*
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-- Run the Simulation
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run -all
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323
pipelined/srt/srt-radix4.sv
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323
pipelined/srt/srt-radix4.sv
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///////////////////////////////////////////
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// srt.sv
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//
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// Written: David_Harris@hmc.edu 13 January 2022
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// Modified:
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//
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// Purpose: Combined Divide and Square Root Floating Point and Integer Unit
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//
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// A component of the Wally configurable RISC-V project.
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//
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// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
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//
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// MIT LICENSE
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// Permission is hereby granted, free of charge, to any person obtaining a copy of this
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// software and associated documentation files (the "Software"), to deal in the Software
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// without restriction, including without limitation the rights to use, copy, modify, merge,
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// publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons
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// to whom the Software is furnished to do so, subject to the following conditions:
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//
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// The above copyright notice and this permission notice shall be included in all copies or
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// substantial portions of the Software.
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//
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// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED,
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// INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR
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// PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
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// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE
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// OR OTHER DEALINGS IN THE SOFTWARE.
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////////////////////////////////////////////////////////////////////////////////////////////////
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`include "wally-config.vh"
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`define DIVLEN ((`NF<(`XLEN)) ? (`XLEN) : `NF)
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module srtradix4 (
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input logic clk,
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input logic Start,
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input logic Stall, // *** multiple pipe stages
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input logic Flush, // *** multiple pipe stages
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// Floating Point Inputs
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// later add exponents, signs, special cases
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input logic XSign, YSign,
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input logic [`NE-1:0] XExp, YExp,
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input logic [`NF-1:0] XFrac, YFrac,
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input logic [`XLEN-1:0] SrcA, SrcB,
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input logic [1:0] Fmt, // Floats: 00 = 16 bit, 01 = 32 bit, 10 = 64 bit, 11 = 128 bit
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input logic W64, // 32-bit ints on XLEN=64
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input logic Signed, // Interpret integers as signed 2's complement
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input logic Int, // Choose integer inputs
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input logic Sqrt, // perform square root, not divide
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output logic rsign,
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output logic [`DIVLEN-1:0] Quot, Rem, // *** later handle integers
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output logic [`NE-1:0] rExp,
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output logic [3:0] Flags
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);
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// logic qp, qz, qm; // quotient is +1, 0, or -1
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logic [3:0] q;
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logic [`NE-1:0] calcExp;
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logic calcSign;
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logic [`DIVLEN-1:0] X, Dpreproc;
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logic [`DIVLEN+3:0] WS, WSA, WSN;
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logic [`DIVLEN+3:0] WC, WCA, WCN;
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logic [`DIVLEN+3:0] D, DBar, D2, DBar2, Dsel;
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logic [$clog2(`XLEN+1)-1:0] intExp;
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logic intSign;
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srtpreproc preproc(SrcA, SrcB, XFrac, YFrac, Fmt, W64, Signed, Int, Sqrt, X, Dpreproc, intExp, intSign);
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// Top Muxes and Registers
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// When start is asserted, the inputs are loaded into the divider.
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// Otherwise, the divisor is retained and the partial remainder
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// is fed back for the next iteration.
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// - assumed one is added here since all numbers are normlaized
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// *** wait what about zero? is that specal case? can the divider handle it?
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// - when the start signal is asserted X and 0 are loaded into WS and WC
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// - otherwise load WSA into the flipflop
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// *** what does N and A stand for?
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// *** change shift amount for radix4
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mux2 #(`DIVLEN+4) wsmux({WSA[`DIVLEN+1:0], 2'b0}, {4'b0001, X}, Start, WSN);
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flop #(`DIVLEN+4) wsflop(clk, WSN, WS);
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mux2 #(`DIVLEN+4) wcmux({WCA[`DIVLEN+1:0], 2'b0}, {`DIVLEN+4{1'b0}}, Start, WCN);
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flop #(`DIVLEN+4) wcflop(clk, WCN, WC);
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flopen #(`DIVLEN+4) dflop(clk, Start, {4'b0001, Dpreproc}, D);
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// Quotient Selection logic
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// Given partial remainder, select quotient of +1, 0, or -1 (qp, qz, pm)
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// *** change this for radix 4 - generate w/ stine code
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// q encoding:
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// 1000 = +2
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// 0100 = +1
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// 0000 = 0
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// 0010 = -1
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// 0001 = -2
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qsel4 qsel4(.D, .WS, .WC, .q);
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// Store the expoenent and sign until division is done
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flopen #(`NE) expflop(clk, Start, calcExp, rExp);
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flopen #(1) signflop(clk, Start, calcSign, rsign);
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// Divisor Selection logic
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// *** radix 4 change to choose -2 to 2
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// - choose the negitive version of what's being selected
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assign DBar = ~D;
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assign DBar2 = {~D[`DIVLEN+2:0], 1'b1};
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assign D2 = {D[`DIVLEN+2:0], 1'b0};
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always_comb
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case (q)
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4'b1000: Dsel = DBar2;
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4'b0100: Dsel = DBar;
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4'b0000: Dsel = {(`DIVLEN+4){1'b0}};
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4'b0010: Dsel = D;
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4'b0001: Dsel = D2;
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default: Dsel = {`DIVLEN+4{1'bx}};
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endcase
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// Partial Product Generation
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// WSA, WCA = WS + WC - qD
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csa #(`DIVLEN+4) csa(WS, WC, Dsel, |q[3:2], WSA, WCA);
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//*** change for radix 4
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otfc4 #(`DIVLEN) otfc4(clk, Start, q, Quot);
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expcalc expcalc(.XExp, .YExp, .calcExp);
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signcalc signcalc(.XSign, .YSign, .calcSign);
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endmodule
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////////////////
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// Submodules //
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////////////////
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///////////////////
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// Preprocessing //
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///////////////////
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module srtpreproc (
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input logic [`XLEN-1:0] SrcA, SrcB,
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input logic [`NF-1:0] XFrac, YFrac,
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input logic [1:0] Fmt, // Floats: 00 = 16 bit, 01 = 32 bit, 10 = 64 bit, 11 = 128 bit
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input logic W64, // 32-bit ints on XLEN=64
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input logic Signed, // Interpret integers as signed 2's complement
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input logic Int, // Choose integer inputs
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input logic Sqrt, // perform square root, not divide
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output logic [`DIVLEN-1:0] X, D,
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output logic [$clog2(`XLEN+1)-1:0] intExp, // Quotient integer exponent
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output logic intSign // Quotient integer sign
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);
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logic [$clog2(`XLEN+1)-1:0] zeroCntA, zeroCntB;
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logic [`XLEN-1:0] PosA, PosB;
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logic [`DIVLEN-1:0] ExtraA, ExtraB, PreprocA, PreprocB, PreprocX, PreprocY;
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assign PosA = (Signed & SrcA[`XLEN - 1]) ? -SrcA : SrcA;
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assign PosB = (Signed & SrcB[`XLEN - 1]) ? -SrcB : SrcB;
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lzc #(`XLEN) lzcA (PosA, zeroCntA);
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lzc #(`XLEN) lzcB (PosB, zeroCntB);
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assign ExtraA = {PosA, {`DIVLEN-`XLEN{1'b0}}};
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assign ExtraB = {PosB, {`DIVLEN-`XLEN{1'b0}}};
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assign PreprocA = ExtraA << zeroCntA;
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assign PreprocB = ExtraB << (zeroCntB + 1);
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assign PreprocX = {XFrac, {`DIVLEN-`NF{1'b0}}};
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assign PreprocY = {YFrac, {`DIVLEN-`NF{1'b0}}};
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assign X = Int ? PreprocA : PreprocX;
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assign D = Int ? PreprocB : PreprocY;
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assign intExp = zeroCntB - zeroCntA + 1;
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assign intSign = Signed & (SrcA[`XLEN - 1] ^ SrcB[`XLEN - 1]);
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endmodule
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/////////////////////////////////
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// Quotient Selection, Radix 2 //
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/////////////////////////////////
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module qsel2 ( // *** eventually just change to 4 bits
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input logic [`DIVLEN+3:`DIVLEN] ps, pc,
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output logic qp, qz, qm
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);
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logic [`DIVLEN+3:`DIVLEN] p, g;
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logic magnitude, sign, cout;
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// The quotient selection logic is presented for simplicity, not
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// for efficiency. You can probably optimize your logic to
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// select the proper divisor with less delay.
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// Quotient equations from EE371 lecture notes 13-20
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assign p = ps ^ pc;
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assign g = ps & pc;
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assign #1 magnitude = ~(&p[`DIVLEN+2:`DIVLEN]);
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assign #1 cout = g[`DIVLEN+2] | (p[`DIVLEN+2] & (g[`DIVLEN+1] | p[`DIVLEN+1] & g[`DIVLEN]));
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assign #1 sign = p[`DIVLEN+3] ^ cout;
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/* assign #1 magnitude = ~((ps[54]^pc[54]) & (ps[53]^pc[53]) &
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(ps[52]^pc[52]));
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assign #1 sign = (ps[55]^pc[55])^
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(ps[54] & pc[54] | ((ps[54]^pc[54]) &
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(ps[53]&pc[53] | ((ps[53]^pc[53]) &
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(ps[52]&pc[52]))))); */
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// Produce quotient = +1, 0, or -1
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assign #1 qp = magnitude & ~sign;
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assign #1 qz = ~magnitude;
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assign #1 qm = magnitude & sign;
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endmodule
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///////////////////////////////////
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// On-The-Fly Converter, Radix 2 //
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///////////////////////////////////
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module otfc4 #(parameter N=65) (
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input logic clk,
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input logic Start,
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input logic [3:0] q,
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output logic [N-1:0] r
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);
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// The on-the-fly converter transfers the quotient
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// bits to the quotient as they come.
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//
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// This code follows the psuedocode presented in the
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// floating point chapter of the book. Right now,
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// it is written for Radix-2 division.
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//
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// QM is Q-1. It allows us to write negative bits
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// without using a costly CPA.
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logic [N+2:0] Q, QM, QNext, QMNext, QMux, QMMux;
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// QR and QMR are the shifted versions of Q and QM.
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// They are treated as [N-1:r] size signals, and
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// discard the r most significant bits of Q and QM.
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logic [N:0] QR, QMR;
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// if starting a new divison set Q to 0 and QM to -1
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mux2 #(N+3) Qmux(QNext, {N+3{1'b0}}, Start, QMux);
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mux2 #(N+3) QMmux(QMNext, {N+3{1'b1}}, Start, QMMux);
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flop #(N+3) Qreg(clk, QMux, Q);
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flop #(N+3) QMreg(clk, QMMux, QM);
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// shift Q (quotent) and QM (quotent-1)
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// if q = 2 Q = {Q, 10} QM = {Q, 01}
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// else if q = 1 Q = {Q, 01} QM = {Q, 00}
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// else if q = 0 Q = {Q, 00} QM = {QM, 11}
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// else if q = -1 Q = {QM, 11} QM = {QM, 10}
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// else if q = -2 Q = {QM, 10} QM = {QM, 01}
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// *** how does the 0 concatination numbers work?
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always_comb begin
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QR = Q[N:0];
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QMR = QM[N:0]; // Shift Q and QM
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if (q[3]) begin // +2
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QNext = {QR, 2'b10};
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QMNext = {QR, 2'b01};
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end else if (q[2]) begin // +1
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QNext = {QR, 2'b01};
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QMNext = {QR, 2'b00};
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end else if (q[1]) begin // -1
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QNext = {QMR, 2'b11};
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QMNext = {QMR, 2'b10};
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end else if (q[0]) begin // -2
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QNext = {QMR, 2'b10};
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QMNext = {QMR, 2'b01};
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end else begin // 0
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QNext = {QR, 2'b00};
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QMNext = {QMR, 2'b11};
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end
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end
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assign r = Q[N+2] ? Q[N+1:2] : Q[N:1];
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endmodule
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/////////
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// csa //
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/////////
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module csa #(parameter N=69) (
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input logic [N-1:0] in1, in2, in3,
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input logic cin,
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output logic [N-1:0] out1, out2
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);
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// This block adds in1, in2, in3, and cin to produce
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// a result out1 / out2 in carry-save redundant form.
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// cin is just added to the least significant bit and
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// is required to handle adding a negative divisor.
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// Fortunately, the carry (out2) is shifted left by one
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// bit, leaving room in the least significant bit to
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// insert cin.
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assign #1 out1 = in1 ^ in2 ^ in3;
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assign #1 out2 = {in1[N-2:0] & (in2[N-2:0] | in3[N-2:0]) |
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(in2[N-2:0] & in3[N-2:0]), cin};
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endmodule
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//////////////
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// expcalc //
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//////////////
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module expcalc(
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input logic [`NE-1:0] XExp, YExp,
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output logic [`NE-1:0] calcExp
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);
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assign calcExp = XExp - YExp + (`NE)'(`BIAS);
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endmodule
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//////////////
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// signcalc //
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//////////////
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module signcalc(
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input logic XSign, YSign,
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output logic calcSign
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);
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assign calcSign = XSign ^ YSign;
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endmodule
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148
pipelined/srt/testbench-radix4.sv
Normal file
148
pipelined/srt/testbench-radix4.sv
Normal file
@ -0,0 +1,148 @@
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`include "wally-config.vh"
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`define DIVLEN ((`NF<`XLEN) ? `XLEN : `NF)
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/////////////
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// counter //
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/////////////
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module counter(input logic clk,
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input logic req,
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output logic done);
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logic [5:0] count;
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// This block of control logic sequences the divider
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// through its iterations. You may modify it if you
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// build a divider which completes in fewer iterations.
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// You are not responsible for the (trivial) circuit
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// design of the block.
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always @(posedge clk)
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begin
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if (count == `DIVLEN/2+1) done <= #1 1;
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else if (done | req) done <= #1 0;
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if (req) count <= #1 0;
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else count <= #1 count+1;
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end
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endmodule
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///////////
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// clock //
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///////////
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module clock(clk);
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output clk;
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// Internal clk signal
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logic clk;
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endmodule
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//////////
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// testbench //
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//////////
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module testbenchradix4;
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logic clk;
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logic req;
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logic done;
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logic [63:0] a, b;
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logic [51:0] afrac, bfrac;
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logic [10:0] aExp, bExp;
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logic asign, bsign;
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logic [51:0] r, rOTFC;
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logic [`DIVLEN-1:0] Quot, QuotOTFC;
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logic [54:0] rp, rm; // positive quotient digits
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// Test parameters
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parameter MEM_SIZE = 40000;
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parameter MEM_WIDTH = 64+64+64;
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`define memr 63:0
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`define memb 127:64
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`define mema 191:128
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// Test logicisters
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logic [MEM_WIDTH-1:0] Tests [0:MEM_SIZE]; // Space for input file
|
||||
logic [MEM_WIDTH-1:0] Vec; // Verilog doesn't allow direct access to a
|
||||
// bit field of an array
|
||||
logic [63:0] correctr, nextr, diffn, diffp;
|
||||
logic [10:0] rExp;
|
||||
logic rsign;
|
||||
integer testnum, errors;
|
||||
|
||||
// Divider
|
||||
srtradix4 srtradix4(.clk, .Start(req),
|
||||
.Stall(1'b0), .Flush(1'b0),
|
||||
.XExp(aExp), .YExp(bExp), .rExp,
|
||||
.XSign(asign), .YSign(bsign), .rsign,
|
||||
.XFrac(afrac), .YFrac(bfrac),
|
||||
.SrcA('0), .SrcB('0), .Fmt(2'b00),
|
||||
.W64(1'b0), .Signed(1'b0), .Int(1'b0), .Sqrt(1'b0),
|
||||
.Quot, .Rem(), .Flags());
|
||||
|
||||
// Counter
|
||||
counter counter(clk, req, done);
|
||||
|
||||
|
||||
initial
|
||||
forever
|
||||
begin
|
||||
clk = 1; #17;
|
||||
clk = 0; #17;
|
||||
end
|
||||
|
||||
|
||||
// Read test vectors from disk
|
||||
initial
|
||||
begin
|
||||
testnum = 0;
|
||||
errors = 0;
|
||||
$readmemh ("testvectors", Tests);
|
||||
Vec = Tests[testnum];
|
||||
a = Vec[`mema];
|
||||
{asign, aExp, afrac} = a;
|
||||
b = Vec[`memb];
|
||||
{bsign, bExp, bfrac} = b;
|
||||
nextr = Vec[`memr];
|
||||
r = Quot[`DIVLEN-1:`DIVLEN - 52];
|
||||
req <= 1;
|
||||
end
|
||||
|
||||
// Apply directed test vectors read from file.
|
||||
|
||||
always @(posedge clk)
|
||||
begin
|
||||
r = Quot[`DIVLEN-1:`DIVLEN - 52];
|
||||
if (done) begin
|
||||
req <= 1;
|
||||
diffp = correctr[51:0] - r;
|
||||
diffn = r - correctr[51:0];
|
||||
if ((rsign !== correctr[63]) | (rExp !== correctr[62:52]) | ($signed(diffn) > 1) | ($signed(diffp) > 1) | (diffn === 64'bx) | (diffp === 64'bx)) // check if accurate to 1 ulp
|
||||
begin
|
||||
errors = errors+1;
|
||||
$display("result was %h_%h, should be %h %h %h\n", rExp, r, correctr, diffn, diffp);
|
||||
$display("failed\n");
|
||||
$stop;
|
||||
end
|
||||
if (afrac === 52'hxxxxxxxxxxxxx)
|
||||
begin
|
||||
$display("%d Tests completed successfully", testnum);
|
||||
$stop;
|
||||
end
|
||||
end
|
||||
if (req)
|
||||
begin
|
||||
req <= 0;
|
||||
correctr = nextr;
|
||||
testnum = testnum+1;
|
||||
Vec = Tests[testnum];
|
||||
$display("a = %h b = %h",a,b);
|
||||
a = Vec[`mema];
|
||||
{asign, aExp, afrac} = a;
|
||||
b = Vec[`memb];
|
||||
{bsign, bExp, bfrac} = b;
|
||||
nextr = Vec[`memr];
|
||||
end
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
||||
Loading…
Reference in New Issue
Block a user