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made testbench-linux's PCDwrong be FlushD

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bbracker 2021-06-25 08:15:19 -04:00
parent 34dbad967d
commit 5b47da21ba
1 changed files with 2 additions and 2 deletions
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wally-pipelined/testbench/testbench-linux.sv
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@ -57,7 +57,7 @@ module testbench();
wallypipelinedsoc dut(.*); wallypipelinedsoc dut(.*);
/////////////////////////////////////////////////////////////////////////////// ///////////////////////////////////////////////////////////////////////////////
//////////////////////// Signals & Shared Macros ////////////////////////// //////////////////////// Signals & Shared Macros ///////////////////////////
//////////////////////// AKA stuff that comes first /////////////////////////// //////////////////////// AKA stuff that comes first ///////////////////////////
/////////////////////////////////////////////////////////////////////////////// ///////////////////////////////////////////////////////////////////////////////
// Sorry if these have gotten decontextualized. // Sorry if these have gotten decontextualized.
@ -252,7 +252,7 @@ module testbench();
// Check if PCD is going to be flushed due to a branch or jump // Check if PCD is going to be flushed due to a branch or jump
if (`BPRED_ENABLED) begin if (`BPRED_ENABLED) begin
PCDwrong = dut.hart.ifu.bpred.bpred.BPPredWrongE; PCDwrong = dut.hart.hzu.FlushD; //Old version: dut.hart.ifu.bpred.bpred.BPPredWrongE; <-- This old version failed to account for MRET.
end else begin end else begin
casex (lastInstrDExpected[31:0]) casex (lastInstrDExpected[31:0])
32'b00000000001000000000000001110011, // URET 32'b00000000001000000000000001110011, // URET