provide time and timeh CSRs based on CLINT's counter

wally-pipelined/src/privileged/csr.sv

@@ -39,6 +39,7 @@ module csr #(parameter
   input  logic             InterruptM,
   input  logic             CSRReadM, CSRWriteM, TrapM, MTrapM, STrapM, UTrapM, mretM, sretM, uretM,
   input  logic             TimerIntM, ExtIntM, SwIntM,
+  input  logic [63:0]      MTIME, MTIMECMP,
   input  logic             InstrValidW, FloatRegWriteW, LoadStallD,
   input  logic 		   BPPredDirWrongM,
   input  logic 		   BTBPredPCWrongM,

wally-pipelined/src/privileged/csrc.sv

@@ -27,10 +27,10 @@
 ///////////////////////////////////////////
 
 `include "wally-config.vh"
-
+// Ben 06/17/21: I brought in MTIME, MTIMECMP from CLINT. *** this probably isn't perfect though because it doesn't yet provide the ability to change these through CSR writes
 module csrc #(parameter 
   MCYCLE = 12'hB00,
-//  MTIME = 12'hB01, // address not specified in privileged spec.  Consider moving to CLINT to match SiFive
+  // MTIME = 12'hB01, // address not specified in privileged spec.  Consider moving to CLINT to match SiFive
   // MTIMECMP = 12'hB21, // not specified in privileged spec.  Move to CLINT
   MINSTRET = 12'hB02,
   MHPMCOUNTERBASE = 12'hB00,
@@ -39,8 +39,8 @@ module csrc #(parameter
   // ... more counters
   //MHPMCOUNTER31 = 12'hB1F,
   MCYCLEH = 12'hB80,
-//  MTIMEH = 12'hB81,  // address not specified in privileged spec.  Consider moving to CLINT to match SiFive
-//  MTIMECMPH = 12'hBA1, // not specified in privileged spec.  Move to CLINT
+  // MTIMEH = 12'hB81,  // address not specified in privileged spec.  Consider moving to CLINT to match SiFive
+  // MTIMECMPH = 12'hBA1, // not specified in privileged spec.  Move to CLINT
   MINSTRETH = 12'hB82,
   MHPMCOUNTERHBASE = 12'hB80,
   //MHPMCOUNTER3H = 12'hB83,
@@ -54,7 +54,7 @@ module csrc #(parameter
   // ... more counters
   //MHPMEVENT31 = 12'h33F,
   CYCLE = 12'hC00, 
-//  TIME = 12'hC01, // not specified
+  TIME = 12'hC01, 
   INSTRET = 12'hC02,
   HPMCOUNTERBASE = 12'hC00,
   //HPMCOUNTER3 = 12'hC03,
@@ -62,7 +62,7 @@ module csrc #(parameter
   //  ...more counters
   //HPMCOUNTER31 = 12'hC1F,
   CYCLEH = 12'hC80,
-//  TIMEH = 12'hC81, // not specified
+  TIMEH = 12'hC81, // not specified
   INSTRETH = 12'hC82,
   HPMCOUNTERHBASE = 12'hC80
   //HPMCOUNTER3H = 12'hC83,
@@ -82,6 +82,7 @@ module csrc #(parameter
     input  logic [1:0]       PrivilegeModeW,
     input  logic [`XLEN-1:0] CSRWriteValM,
     input  logic [31:0]      MCOUNTINHIBIT_REGW, MCOUNTEREN_REGW, SCOUNTEREN_REGW,
+    input  logic [63:0]      MTIME, MTIMECMP,
     output logic [`XLEN-1:0] CSRCReadValM,
     output logic             IllegalCSRCAccessM
   );
@@ -112,12 +113,12 @@ module csrc #(parameter
 
       // Counter adders with inhibits for power savings
       assign CYCLEPlusM = CYCLE_REGW + {63'b0, ~MCOUNTINHIBIT_REGW[0]};
-    //  assign TIMEPlusM = TIME_REGW + 1; // can't be inhibited
+      //assign TIMEPlusM = TIME_REGW + 1; // can't be inhibited
       assign INSTRETPlusM = INSTRET_REGW + {63'b0, InstrValidW & ~MCOUNTINHIBIT_REGW[2]};
       //assign HPMCOUNTER3PlusM = HPMCOUNTER3_REGW + {63'b0, LoadStallD & ~MCOUNTINHIBIT_REGW[3]}; // count load stalls
-      ///assign HPMCOUNTER4PlusM = HPMCOUNTER4_REGW + {63'b0, 1'b0 & ~MCOUNTINHIBIT_REGW[4]}; // change to count signals
+      //assign HPMCOUNTER4PlusM = HPMCOUNTER4_REGW + {63'b0, 1'b0 & ~MCOUNTINHIBIT_REGW[4]}; // change to count signals
       assign NextCYCLEM = WriteCYCLEM ? CSRWriteValM : CYCLEPlusM[`XLEN-1:0];
-    //  assign NextTIMEM = WriteTIMEM ? CSRWriteValM : TIMEPlusM[`XLEN-1:0];
+      //assign NextTIMEM = WriteTIMEM ? CSRWriteValM : TIMEPlusM[`XLEN-1:0];
       assign NextINSTRETM = WriteINSTRETM ? CSRWriteValM : INSTRETPlusM[`XLEN-1:0];
       //assign NextHPMCOUNTER3M = WriteHPMCOUNTER3M ? CSRWriteValM : HPMCOUNTER3PlusM[`XLEN-1:0]; 
       //assign NextHPMCOUNTER4M = WriteHPMCOUNTER4M ? CSRWriteValM : HPMCOUNTER4PlusM[`XLEN-1:0];
@@ -211,7 +212,7 @@ module csrc #(parameter
           //flopr   #(32) HPMCOUNTER4Hreg(clk, reset, NextHPMCOUNTER4HM, HPMCOUNTER4_REGW[63:32]);
         end
 
-    // eventually move TIME and TIMECMP to the CLINT
+    // eventually move TIME and TIMECMP to the CLINT -- Ben 06/17/21: sure let's give that a shot!
     //  run TIME off asynchronous reference clock
     //  synchronize write enable to TIME
     //  four phase handshake to synchronize reads from TIME
@@ -235,7 +236,7 @@ module csrc #(parameter
                 MINSTRET:     CSRCReadValM = INSTRET_REGW;
                 //MHPMCOUNTER3: CSRCReadValM = HPMCOUNTER3_REGW;
                 //MHPMCOUNTER4: CSRCReadValM = HPMCOUNTER4_REGW;
-      //          TIME:         CSRCReadValM = TIME_REGW;
+                TIME:         CSRCReadValM = MTIME;
                 CYCLE:        CSRCReadValM = CYCLE_REGW;
                 INSTRET:      CSRCReadValM = INSTRET_REGW;
                 //HPMCOUNTER3:  CSRCReadValM = HPMCOUNTER3_REGW;
@@ -275,7 +276,7 @@ module csrc #(parameter
                 MINSTRETH:     CSRCReadValM = INSTRET_REGW[63:32];
                 //MHPMCOUNTER3H: CSRCReadValM = HPMCOUNTER3_REGW[63:32];
                 //MHPMCOUNTER4H: CSRCReadValM = HPMCOUNTER4_REGW[63:32];
-      //          TIMEH:         CSRCReadValM = TIME_REGW[63:32];
+                TIMEH:         CSRCReadValM = MTIME[63:32];
                 CYCLEH:        CSRCReadValM = CYCLE_REGW[63:32];
                 INSTRETH:      CSRCReadValM = INSTRET_REGW[63:32];
                 //HPMCOUNTER3H:  CSRCReadValM = HPMCOUNTER3_REGW[63:32];

wally-pipelined/src/privileged/privileged.sv

@@ -52,6 +52,7 @@ module privileged (
   input  logic             LoadMisalignedFaultM,
   input  logic             StoreMisalignedFaultM,
   input  logic             TimerIntM, ExtIntM, SwIntM,
+  input  logic [63:0]      MTIME, MTIMECMP,
   input  logic [`XLEN-1:0] InstrMisalignedAdrM, MemAdrM,
   input  logic [4:0]       SetFflagsM,
 

wally-pipelined/src/uncore/clint.sv

@@ -36,9 +36,9 @@ module clint (
   input  logic [1:0]       HTRANS,
   output logic [`XLEN-1:0] HREADCLINT,
   output logic             HRESPCLINT, HREADYCLINT,
+  output logic [63:0]      MTIME, MTIMECMP,
   output logic             TimerIntM, SwIntM);
 
-  logic [63:0] MTIMECMP, MTIME;
   logic        MSIP;
 
   logic [15:0] entry, entryd;

wally-pipelined/src/uncore/uncore.sv

@@ -57,7 +57,8 @@ module uncore (
   input  logic [31:0]      GPIOPinsIn,
   output logic [31:0]      GPIOPinsOut, GPIOPinsEn, 
   input  logic             UARTSin,
-  output logic             UARTSout
+  output logic             UARTSout,
+  output logic [63:0]      MTIME, MTIMECMP
 );
   
   logic [`XLEN-1:0] HWDATA;

wally-pipelined/src/wally/wallypipelinedhart.sv

@@ -34,6 +34,7 @@ module wallypipelinedhart (
   input  logic             TimerIntM, ExtIntM, SwIntM,
   input  logic             InstrAccessFaultF, 
   input  logic             DataAccessFaultM,
+  input  logic [63:0]      MTIME, MTIMECMP,
   // Bus Interface
   input  logic [15:0]      rd2, // bogus, delete when real multicycle fetch works
   input  logic [`AHBW-1:0] HRDATA,

wally-pipelined/src/wally/wallypipelinedsoc.sv

@@ -63,6 +63,7 @@ module wallypipelinedsoc (
   logic [5:0]       HSELRegions;
   logic             InstrAccessFaultF, DataAccessFaultM;
   logic             TimerIntM, SwIntM; // from CLINT
+  logic [63:0]      MTIME, MTIMECMP; // from CLINT to CSRs
   logic             ExtIntM; // from PLIC
   logic [2:0]       HADDRD;
   logic [3:0]       HSIZED;