forked from Github_Repos/cvw
Updated trap handler to check interrupt vectoring before handling them and to use the mscratch instead of sp for a stack.
This commit is contained in:
Kip Macsai-Goren
parent
3268f27f7a
commit
590b86147b
@ -41,7 +41,7 @@ RVTEST_CODE_BEGIN
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//
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// Initialize x6 as a virtual pointer to the test results
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// Initialize x16 as a physical pointer to the test results
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// Set up stack pointer (sp = x2)
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// Set up stack pointer, mscratch, sscratch
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//
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// ---------------------------------------------------------------------------------------------
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@ -50,8 +50,12 @@ RVTEST_CODE_BEGIN
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la x16, test_1_res // x16 reserved for the physical address equivalent of x6 to be used in trap handlers
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// any time either is used, both must be updated.
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// address for stack
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la sp, top_of_stack
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// address for normal user stack, mscratch stack, and sscratch stack
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la sp, mscratch_top
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csrw mscratch, sp
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la sp, sscratch_top
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csrw sscratch, sp
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la sp, stack_top
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.endm
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@ -72,7 +76,7 @@ cause_instr_addr_misaligned:
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cause_instr_access:
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la x28, 0x0 // address zero is an address with no memory
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sd x1, -8(sp) // push the return adress ontot the stack
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sd x1, -8(sp) // push the return adress onto the stack
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addi sp, sp, -8
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jalr x28 // cause instruction access trap
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ld x1, 0(sp) // pop return adress back from the stack
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@ -83,7 +87,7 @@ cause_illegal_instr:
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.word 0x00000000 // a 32 bit zros is an illegal instruction
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ret
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cause_breakpnt: // ****
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cause_breakpnt:
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ebreak
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ret
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@ -128,7 +132,9 @@ cause_time_interrupt:
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sw x31,4(x29) // store into most significant word of MTIMECMP
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nowrap:
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sw x28, 0(x29) // store into least significant word of MTIMECMP
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loop: j loop // wait until interrupt occurs
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loop:
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wfi
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j loop // wait until interrupt occurs
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ret
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cause_soft_interrupt:
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@ -150,7 +156,7 @@ end_trap_triggers:
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.macro TRAP_HANDLER MODE, VECTORED=1, DEBUG=0
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// MODE decides which mode this trap handler will be taken in (M or S mode)
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// Vectored decides whether interrumpts are handled with the vector table at trap_handler_MODE (1)
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// Vectored decides whether interrupts are handled with the vector table at trap_handler_MODE (1)
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// vs Using the non-vector approach the rest of the trap handler takes (0)
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// DEBUG decides whether we will print mtval a string with status.mpie, status.mie, and status.mpp to the signature (1)
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// vs not saving that info to the signature (0)
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@ -216,23 +222,28 @@ trap_handler_\MODE\():
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// *** ASSUMES that a cause value of 0 for an interrupt is unimplemented
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// otherwise, a vectored interrupt handler should jump to trap_handler_\MODE\() + 4 * Interrupt cause code
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// No matter the value of VECTORED, exceptions (not interrupts) are handled in an unvecotred way
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j soft_interrupt_\MODE\() // 1: instruction access fault // the zero spot is taken up by the instruction to skip this table.
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j s_soft_vector_\MODE\() // 1: instruction access fault // the zero spot is taken up by the instruction to skip this table.
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j segfault_\MODE\() // 2: reserved
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j soft_interrupt_\MODE\() // 3: breakpoint
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j m_soft_vector_\MODE\() // 3: breakpoint
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j segfault_\MODE\() // 4: reserved
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j time_interrupt_\MODE\() // 5: load access fault
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j s_time_vector_\MODE\() // 5: load access fault
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j segfault_\MODE\() // 6: reserved
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j time_interrupt_\MODE\() // 7: store access fault
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j m_time_vector_\MODE\() // 7: store access fault
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j segfault_\MODE\() // 8: reserved
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j ext_interrupt_\MODE\() // 9: ecall from S-mode
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j s_ext_vector_\MODE\() // 9: ecall from S-mode
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j segfault_\MODE\() // 10: reserved
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j ext_interrupt_\MODE\() // 11: ecall from M-mode
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j m_ext_vector_\MODE\() // 11: ecall from M-mode
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// 12 through >=16 are reserved or designated for platform use
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trap_unvectored_\MODE\():
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csrrw sp, \MODE\()scratch, sp // swap sp and scratch so we can use the scratch stack in the trap hanler without messing up sp's value or the stack itself.
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// *** NOTE: this means that nested traps will be screwed up but they shouldn't happen in any of these tests
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trap_stack_saved_\MODE\(): // jump here after handling vectored interupt since we already switch sp and scratch there
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// save registers on stack before using
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sd x1, -8(sp)
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sd x5, -16(sp)
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sd x7, -24(sp)
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// Record trap
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csrr x1, \MODE\()cause // record the mcause
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@ -262,49 +273,35 @@ trap_unvectored_\MODE\():
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// Respond to trap based on cause
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// All interrupts should return after being logged
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csrr x1, \MODE\()cause
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slli x1, x1, 3 // multiply cause by 8 to get offset in vector Table
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li x5, 0x8000000000000000 // if msb is set, it is an interrupt
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and x5, x5, x1
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bnez x5, trapreturn_\MODE\() // return from interrupt
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bnez x5, interrupt_handler_\MODE\() // return from interrupt
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// Other trap handling is specified in the vector Table
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slli x1, x1, 3 // multiply cause by 8 to get offset in vector Table
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la x5, exception_vector_table_\MODE\()
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add x5, x5, x1 // compute address of vector in Table
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ld x5, 0(x5) // fectch address of handler from vector Table
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jr x5 // and jump to the handler
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interrupt_handler_\MODE\():
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la x5, interrupt_vector_table_\MODE\() // NOTE THIS IS NOT THE SAME AS VECTORED INTERRUPTS!!!
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add x5, x5, x1 // compute address of vector in Table
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ld x5, 0(x5) // fectch address of handler from vector Table
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jr x5 // and jump to the handler
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segfault_\MODE\():
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ld x5, -16(sp) // restore registers from stack before faulting
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sd x7, -24(sp) // restore registers from stack before faulting
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ld x5, -16(sp)
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ld x1, -8(sp)
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j terminate_test // halt program.
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trapreturn_\MODE\():
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// look at the instruction to figure out whether to add 2 or 4 bytes to PC, or go to address specified in a1
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csrr x1, \MODE\()epc // get the mepc
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addi x1, x1, 4 // *** should be 2 for compressed instructions, see note.
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// ****** KMG: the following is no longer as easy to determine. mepc gets the virtual address of the trapped instruction,
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// ******** but in the handler, we work in M mode with physical addresses
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// This means the address in mepc is suddenly pointing somewhere else.
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// to get this to work, We could either retranslate the vaddr back into a paddr (probably on the scale of difficult to intractible)
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// or we could come up with some other ingenious way to stay in M mode and see if the instruction was compressed.
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// lw x5, 0(x1) // read the faulting instruction
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// li x1, 3 // check bottom 2 bits of instruction to see if compressed
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// and x5, x5, x1 // mask the other bits
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// beq x5, x1, trapreturn_uncompressed_\MODE\() // if 11, the instruction is return_uncompressed
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// trapreturn_compressed_\MODE\():
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// csrr x1, mepc // get the mepc again
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// addi x1, x1, 2 // add 2 to find the next instruction
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// j trapreturn_specified_\MODE\() // and return
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// trapreturn_uncompressed_\MODE\():
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// csrr x1, mepc // get the mepc again
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// addi x1, x1, 4 // add 4 to find the next instruction
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csrr x1, \MODE\()epc
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addi x1, x1, 4 // return to the address AFTER the trapping instruction
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trapreturn_specified_\MODE\():
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// reset the necessary pointers and registers (x1, x5, x6, and the return address going to mepc)
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// note that we don't need to change x7 since it was a temporary register with no important address in it.
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// so that when we return to a new virtual address, they're all in the right spot as well.
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beqz a1, trapreturn_finished_\MODE\() // either update values, of go to default return address.
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@ -318,13 +315,13 @@ trapreturn_specified_\MODE\():
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sll x5, x5, a2
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addi x5, x5, -1 // x5 = mask bits for offset into current pagetype
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// reset the top of the stack, x1
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// reset the top of the stack, which will be put into ra
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ld x7, -8(sp)
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and x7, x5, x7 // x7 = offset for x1
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add x7, x7, a1 // x7 = new address for x1
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sd x7, -8(sp)
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// reset the second spot in the stack, x5
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// reset the second spot in the stack, which will be put into x5
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ld x7, -16(sp)
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and x7, x5, x7 // x7 = offset for x5
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add x7, x7, a1 // x7 = new address for x5
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@ -334,7 +331,7 @@ trapreturn_specified_\MODE\():
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and x7, x5, x6 // x7 = offset for x6
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add x6, x7, a1 // x6 = new address for the result pointer
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// set return address, stored temporarily in x1, to the next instruction, but in the new virtual page.
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// reset x1, which temporarily holds the return address that will be written to mepc.
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and x1, x5, x1 // x1 = offset for the return address
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add x1, x1, a1 // x1 = new return address.
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@ -342,10 +339,10 @@ trapreturn_specified_\MODE\():
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li a2, 0 // reset trapreturn inputs to the trap handler
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trapreturn_finished_\MODE\():
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csrw \MODE\()epc, x1 // update the epc with address of next instruction
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ld x5, -16(sp) // restore registers from stack before returning
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csrw \MODE\()epc, x1 // update the epc with address of next instruction
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ld x7, -24(sp) // restore registers from stack before returning
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ld x5, -16(sp)
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ld x1, -8(sp)
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// *** this should be handled by indirectly clearing this bit csrw \MODE\()ip, 0x0 // clear interrupt pending register to indicate interrupt has been handled
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\MODE\()ret // return from trap
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ecallhandler_\MODE\():
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@ -380,18 +377,17 @@ ecallhandler_changetousermode_\MODE\():
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j trapreturn_\MODE\()
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instrpagefault_\MODE\():
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ld x1, -8(sp) // load return address int x1 (the address AFTER the jal to the faulting address)
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ld x1, -8(sp) // load return address from stack into ra (the address AFTER the jal to the faulting address)
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j trapreturn_finished_\MODE\() // puts x1 into mepc, restores stack and returns to program (outside of faulting page)
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instrfault_\MODE\():
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ld x1, -8(sp) // load return address int x1 (the address AFTER the jal to the faulting address)
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j trapreturn_finished_\MODE\() // return to the code after recording the mcause
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ld x1, -8(sp) // load return address from stack into ra (the address AFTER the jal to the faulting address)
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j trapreturn_finished_\MODE\() // return to the code at ra value from before trap
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illegalinstr_\MODE\():
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j trapreturn_\MODE\() // return to the code after recording the mcause
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accessfault_\MODE\():
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// *** What do I have to do here?
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j trapreturn_\MODE\()
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addr_misaligned_\MODE\():
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@ -400,36 +396,67 @@ addr_misaligned_\MODE\():
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breakpt_\MODE\():
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j trapreturn_\MODE\()
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soft_interrupt_\MODE\():
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li x5, 0x7EC // write 0x7EC (looks like VEC) to the output before the mcause and extras to indicate that this trap was handled with a vector table.
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sd x5, 0(x16)
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s_soft_vector_\MODE\():
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csrrw sp, \MODE\()scratch, sp // swap sp and scratch so we can use the scratch stack in the trap hanler without messing up sp's value or the stack itself.
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sd x5, -8(sp) // put x5 on the scratch stack before messing with it
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li x5, 0x7EC01 // write 0x7ec01 (for "VEC"tored and 01 for the interrupt code)
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j vectored_int_end_\MODE\()
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m_soft_vector_\MODE\():
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csrrw sp, \MODE\()scratch, sp // swap sp and scratch so we can use the scratch stack in the trap hanler without messing up sp's value or the stack itself.
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sd x5, -8(sp) // put x5 on the scratch stack before messing with it
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li x5, 0x7EC03 // write 0x7ec03 (for "VEC"tored and 03 for the interrupt code)
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j vectored_int_end_\MODE\()
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s_time_vector_\MODE\():
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csrrw sp, \MODE\()scratch, sp // swap sp and scratch so we can use the scratch stack in the trap hanler without messing up sp's value or the stack itself.
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sd x5, -8(sp) // put x5 on the scratch stack before messing with it
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li x5, 0x7EC05 // write 0x7ec05 (for "VEC"tored and 05 for the interrupt code)
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j vectored_int_end_\MODE\()
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m_time_vector_\MODE\():
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csrrw sp, \MODE\()scratch, sp // swap sp and scratch so we can use the scratch stack in the trap hanler without messing up sp's value or the stack itself.
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sd x5, -8(sp) // put x5 on the scratch stack before messing with it
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li x5, 0x7EC07 // write 0x7ec07 (for "VEC"tored and 07 for the interrupt code)
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j vectored_int_end_\MODE\()
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s_ext_vector_\MODE\():
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csrrw sp, \MODE\()scratch, sp // swap sp and scratch so we can use the scratch stack in the trap hanler without messing up sp's value or the stack itself.
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sd x5, -8(sp) // put x5 on the scratch stack before messing with it
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li x5, 0x7EC09 // write 0x7ec09 (for "VEC"tored and 08 for the interrupt code)
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j vectored_int_end_\MODE\()
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m_ext_vector_\MODE\():
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csrrw sp, \MODE\()scratch, sp // swap sp and scratch so we can use the scratch stack in the trap hanler without messing up sp's value or the stack itself.
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sd x5, -8(sp) // put x5 on the scratch stack before messing with it
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li x5, 0x7EC0B // write 0x7ec0B (for "VEC"tored and 0B for the interrupt code)
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j vectored_int_end_\MODE\()
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vectored_int_end_\MODE\():
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sd x5, 0(x16) // store to signature to show vectored interrupts succeeded.
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addi x6, x6, 8
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addi x16, x16, 8
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ld x5, -8(sp) // restore x5 before continuing to handle trap in case its needed.
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j trap_stack_saved_\MODE\()
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soft_interrupt_\MODE\():
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la x28, 0x02000000 // Reset by clearing MSIP interrupt from CLINT
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sw x0, 0(x28)
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j trap_unvectored_\MODE\()
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j trapreturn_\MODE\()
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time_interrupt_\MODE\():
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li x5, 0x7EC
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sd x5, 0(x16)
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addi x6, x6, 8
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addi x16, x16, 8
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la x29, 0x02004000 // MTIMECMP register in CLINT
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li x30, 0xFFFFFFFF
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sd x30, 0(x29) // reset interrupt by setting mtimecmp to 0xFFFFFFFF
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j trap_unvectored_\MODE\()
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ld x1, -8(sp) // load return address from stack into ra (the address AFTER the jal to the faulting address)
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j trapreturn_finished_\MODE\() // return to the code at ra value from before trap
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ext_interrupt_\MODE\():
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li x5, 0x7EC
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sd x5, 0(x16)
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addi x6, x6, 8
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addi x16, x16, 8
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li x28, 0x10060000 // reset interrupt by clearing all the GPIO bits
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sw x0, 8(x28) // disable the first pin as an output
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sw x0, 40(x28) // write a 0 to the first output pin (reset interrupt)
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j trap_unvectored_\MODE\()
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j trapreturn_\MODE\()
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// Table of trap behavior
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// lists what to do on each exception (not interrupts)
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@ -455,6 +482,21 @@ exception_vector_table_\MODE\():
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.8byte segfault_\MODE\() // 14: reserved
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.8byte trapreturn_\MODE\() // 15: store page fault
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.align 3 // aligns this data table to an 8 byte boundary
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interrupt_vector_table_\MODE\():
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.8byte segfault_\MODE\() // 0: reserved
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.8byte s_soft_vector_\MODE\() // 1: instruction access fault // the zero spot is taken up by the instruction to skip this table.
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.8byte segfault_\MODE\() // 2: reserved
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.8byte m_soft_vector_\MODE\() // 3: breakpoint
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.8byte segfault_\MODE\() // 4: reserved
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.8byte s_time_vector_\MODE\() // 5: load access fault
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.8byte segfault_\MODE\() // 6: reserved
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.8byte m_time_vector_\MODE\() // 7: store access fault
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.8byte segfault_\MODE\() // 8: reserved
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.8byte s_ext_vector_\MODE\() // 9: ecall from S-mode
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.8byte segfault_\MODE\() // 10: reserved
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.8byte m_ext_vector_\MODE\() // 11: ecall from M-mode
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.align 3
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trap_return_pagetype_table_\MODE\():
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.8byte 0xC // 0: kilopage has 12 offset bits
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@ -1051,9 +1093,20 @@ rvtest_data:
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RVTEST_DATA_END
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.align 3 // align stack to 8 byte boundary
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bottom_of_stack:
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stack_bottom:
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.fill 1024, 4, 0xdeadbeef
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top_of_stack:
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stack_top:
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.align 3
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mscratch_bottom:
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.fill 512, 4, 0xdeadbeef
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mscratch_top:
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.align 3
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sscratch_bottom:
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.fill 512, 4, 0xdeadbeef
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sscratch_top:
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RVMODEL_DATA_BEGIN
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