Xavi/cvw
1
0
Fork 0
forked from Github_Repos/cvw
Code Issues Pull Requests Packages Projects Releases Wiki Activity

Refactored setup QUESTA and SNPS paths, and removed troublesome bit manipulation test cases

Browse Source
This commit is contained in:
David Harris 2023-01-23 05:00:11 -08:00
parent 79d041a135
commit 58a973ec97
3 changed files with 9 additions and 6 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

9
setup.sh
View File

@ -2,7 +2,7 @@
# setup.sh
# David_Harris@hmc.edu and kekim@hmc.edu 1 December 2021
# Set up tools for riscv-wally
# Set up tools for rvw
echo "Executing Wally setup.sh"
@ -15,14 +15,15 @@ echo \$WALLY set to ${WALLY}
# Must edit these based on your local environment. Ask your sysadmin.
export MGLS_LICENSE_FILE=1717@solidworks.eng.hmc.edu # Change this to your Siemens license server
export SNPSLMD_LICENSE_FILE=27020@zircon.eng.hmc.edu # Change this to your Synopsys license server
export PATH=/cad/mentor/questa_sim-2021.2_1/questasim/bin:$PATH # Change this for your path to Questa
export PATH=/cad/synopsys/SYN/bin:$PATH # Change this for your path to Design Compiler
export QUESTAPATH=/cad/mentor/questa_sim-2021.2_1/questasim/bin # Change this for your path to Questa
export SNPSPATH=/cad/synopsys/SYN/bin # Change this for your path to Design Compiler
# Path to RISC-V Tools
export RISCV=/opt/riscv # change this if you installed the tools in a different location
# Tools
# Questa and Synopsys
export PATH=$QUESTAPATH:$SNPSPATH:$PATH
# GCC
export LD_LIBRARY_PATH=$LD_LIBRARY_PATH:$RISCV/riscv-gnu-toolchain/lib:$RISCV/riscv-gnu-toolchain/riscv64-unknown-elf/lib
export PATH=$PATH:$RISCV/riscv-gnu-toolchain/bin:$RISCV/riscv-gnu-toolchain/riscv64-unknown-elf/bin # GCC tools

3
tests/riscof/spike/spike_rv32imc_isa.yaml
View File

@ -1,6 +1,7 @@
hart_ids: [0]
hart0:
ISA: RV32IMAFDCZicsr_Zifencei_Zba_Zbb_Zbc_Zbs
ISA: RV32IMAFDCZicsr_Zifencei
# ISA: RV32IMAFDCZicsr_Zifencei_Zba_Zbb_Zbc_Zbs
physical_addr_sz: 32
User_Spec_Version: '2.3'
supported_xlen: [32]

3
tests/riscof/spike/spike_rv64gc_isa.yaml
View File

@ -1,6 +1,7 @@
hart_ids: [0]
hart0:
ISA: RV64IMAFDCSUZicsr_Zifencei_Zba_Zbb_Zbc_Zbs
ISA: RV64IMAFDCSUZicsr_Zifencei
# ISA: RV64IMAFDCSUZicsr_Zifencei_Zba_Zbb_Zbc_Zbs
physical_addr_sz: 56
User_Spec_Version: '2.3'
supported_xlen: [64]