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abs for int inputs

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cturek 2022-10-26 16:18:05 +00:00
parent e401d12889
commit 544c142c4f
1 changed files with 11 additions and 6 deletions
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17
pipelined/src/fpu/fdivsqrt/fdivsqrtpreproc.sv
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@ -46,16 +46,17 @@ module fdivsqrtpreproc (
output logic [`DIVb+3:0] X, output logic [`DIVb+3:0] X,
output logic [`DIVN-2:0] Dpreproc output logic [`DIVN-2:0] Dpreproc
); );
// logic [`XLEN-1:0] PosA, PosB;
// logic [`DIVLEN-1:0] ExtraA, ExtraB, PreprocA, PreprocB, PreprocX, PreprocY; // logic [`DIVLEN-1:0] ExtraA, ExtraB, PreprocA, PreprocB, PreprocX, PreprocY;
logic [`NF-1:0] PreprocA, PreprocX; logic [`NF-1:0] PreprocA, PreprocX;
logic [`NF-1:0] PreprocB, PreprocY; logic [`NF-1:0] PreprocB, PreprocY;
// logic [`DIVN-1:0] ZeroBufX, ZeroBufY; add after Cedar Commit
logic [`NF+1:0] SqrtX; logic [`NF+1:0] SqrtX;
logic [`DIVb+3:0] DivX; logic [`DIVb+3:0] DivX;
logic [$clog2(`NF+2)-1:0] XZeroCnt, YZeroCnt; logic [$clog2(`NF+2)-1:0] XZeroCnt, YZeroCnt;
logic [`NE+1:0] Qe; logic [`NE+1:0] Qe;
logic Signed; // Intdiv signals
// logic [`DIVN-1:0] ZeroBufX, ZeroBufY; add after Cedar Commit
logic [`XLEN-1:0] PosA, PosB;
logic Signed, Aneg, Bneg;
// ***can probably merge X LZC with conversion // ***can probably merge X LZC with conversion
// cout the number of leading zeros // cout the number of leading zeros
@ -66,6 +67,10 @@ module fdivsqrtpreproc (
lzc #(`NF+1) lzcY (Ym, YZeroCnt); lzc #(`NF+1) lzcY (Ym, YZeroCnt);
assign Signed = Funct3E[0]; assign Signed = Funct3E[0];
assign Aneg = ForwardedSrcAE[`XLEN-1] & Signed;
assign Bneg = ForwardedSrcBE[`XLEN-1] & Signed;
assign PosA = Aneg ? -ForwardedSrcAE : ForwardedSrcAE;
assign PosB = Bneg ? -ForwardedSrcBE : ForwardedSrcBE;
assign PreprocX = Xm[`NF-1:0]<<XZeroCnt; assign PreprocX = Xm[`NF-1:0]<<XZeroCnt;
assign PreprocY = Ym[`NF-1:0]<<YZeroCnt; assign PreprocY = Ym[`NF-1:0]<<YZeroCnt;