trap comments

pipelined/src/privileged/privmode.sv

@@ -4,7 +4,7 @@
 // Written: David_Harris@hmc.edu 12 May 2022
 // Modified: 
 //
-// Purpose: Track privilege mode
+// Purpose: Track privilege mode.  Change on traps and returns.
 // 
 // Documentation: RISC-V System on Chip Design Chapter 5
 //
@@ -30,11 +30,14 @@
 
 module privmode (
   input  logic             clk, reset,
-  input  logic             StallW, TrapM, mretM, sretM,
+  input  logic             StallW, 
-  input  logic             DelegateM,
+  input  logic             TrapM,               // Trap 
-  input  logic [1:0]       STATUS_MPP,
+  input  logic             mretM, sretM,        // return instruction
-  input  logic             STATUS_SPP,
+  input  logic             DelegateM,           // trap delegated to supervisor mode
-  output logic [1:0]       NextPrivilegeModeM, PrivilegeModeW
+  input  logic [1:0]       STATUS_MPP,          // machine trap previous privilege mode
+  input  logic             STATUS_SPP,          // supervisor trap previous privilege mode
+  output logic [1:0]       NextPrivilegeModeM,  // next privilege mode, used when updating STATUS CSR on a trap
+  output logic [1:0]       PrivilegeModeW       // current privilege mode
 ); 
   
   if (`U_SUPPORTED) begin:privmode
@@ -44,7 +47,7 @@ module privmode (
         if (`S_SUPPORTED & DelegateM) NextPrivilegeModeM = `S_MODE;
         else                          NextPrivilegeModeM = `M_MODE;
       end else if (mretM)             NextPrivilegeModeM = STATUS_MPP;
-      else if (sretM)                 NextPrivilegeModeM = {1'b0, STATUS_SPP};
+      else     if (sretM)             NextPrivilegeModeM = {1'b0, STATUS_SPP};
       else                            NextPrivilegeModeM = PrivilegeModeW;
     end
 

pipelined/src/privileged/privpiperegs.sv

@@ -29,18 +29,19 @@
 `include "wally-config.vh"
 
 module privpiperegs (
-  input  logic         clk, reset,
+  input  logic         clk, reset,  
   input  logic         StallD, StallE, StallM,
   input  logic         FlushD, FlushE, FlushM,
-  input  logic         InstrPageFaultF, InstrAccessFaultF,
+  input  logic         InstrPageFaultF, InstrAccessFaultF,  // instruction faults
-  input  logic         IllegalIEUInstrFaultD,
+  input  logic         IllegalIEUInstrFaultD,               // illegal IEU instruction decoded
-  output logic         InstrPageFaultM, InstrAccessFaultM,
+  output logic         InstrPageFaultM, InstrAccessFaultM,  // delayed instruction faults
-  output logic         IllegalIEUInstrFaultM
+  output logic         IllegalIEUInstrFaultM                // delayed illegal IEU instruction
 );
 
-  logic InstrPageFaultD, InstrAccessFaultD;
+  // Delayed fault signals
-  logic InstrPageFaultE, InstrAccessFaultE;
+  logic                InstrPageFaultD, InstrAccessFaultD;
-  logic IllegalIEUInstrFaultE; 
+  logic                InstrPageFaultE, InstrAccessFaultE;
+  logic                IllegalIEUInstrFaultE; 
 
   // pipeline fault signals
   flopenrc #(2) faultregD(clk, reset, FlushD, ~StallD,