forked from Github_Repos/cvw
Cache cleanup.
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parent
41a79556e0
commit
529d8b629a
36
pipelined/src/cache/cachefsm.sv
vendored
36
pipelined/src/cache/cachefsm.sv
vendored
@ -140,9 +140,7 @@ module cachefsm
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// *** Ross simplify: factor out next state and output logic
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// *** Ross simplify: factor out next state and output logic
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always_comb begin
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always_comb begin
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PreSelAdr = 2'b00;
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PreSelAdr = 2'b00;
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LRUWriteEn = 1'b0;
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//SelFlush = 1'b0;
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SelFlush = 1'b0;
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FlushAdrCntEn = 1'b0;
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FlushWayCntEn = 1'b0;
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FlushWayCntEn = 1'b0;
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FlushAdrCntRst = 1'b0;
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FlushAdrCntRst = 1'b0;
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FlushWayCntRst = 1'b0;
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FlushWayCntRst = 1'b0;
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@ -156,7 +154,6 @@ module cachefsm
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STATE_READY: begin
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STATE_READY: begin
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PreSelAdr = 2'b00;
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PreSelAdr = 2'b00;
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LRUWriteEn = 1'b0;
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// TLB Miss
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// TLB Miss
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if(IgnoreRequest) begin
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if(IgnoreRequest) begin
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@ -180,7 +177,6 @@ module cachefsm
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// amo hit
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// amo hit
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else if(Atomic[1] & (&RW) & CacheHit) begin
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else if(Atomic[1] & (&RW) & CacheHit) begin
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PreSelAdr = 2'b01;
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PreSelAdr = 2'b01;
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LRUWriteEn = 1'b1;
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if(CPUBusy) begin
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if(CPUBusy) begin
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NextState = STATE_CPU_BUSY_FINISH_AMO;
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NextState = STATE_CPU_BUSY_FINISH_AMO;
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@ -193,7 +189,6 @@ module cachefsm
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end
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end
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// read hit valid cached
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// read hit valid cached
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else if(RW[1] & CacheHit) begin
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else if(RW[1] & CacheHit) begin
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LRUWriteEn = 1'b1;
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if(CPUBusy) begin
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if(CPUBusy) begin
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NextState = STATE_CPU_BUSY;
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NextState = STATE_CPU_BUSY;
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@ -207,7 +202,6 @@ module cachefsm
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// write hit valid cached
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// write hit valid cached
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else if (RW[0] & CacheHit) begin
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else if (RW[0] & CacheHit) begin
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PreSelAdr = 2'b01;
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PreSelAdr = 2'b01;
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LRUWriteEn = 1'b1;
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if(CPUBusy) begin
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if(CPUBusy) begin
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NextState = STATE_CPU_BUSY;
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NextState = STATE_CPU_BUSY;
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@ -264,7 +258,6 @@ module cachefsm
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end
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end
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STATE_MISS_READ_WORD_DELAY: begin
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STATE_MISS_READ_WORD_DELAY: begin
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LRUWriteEn = 1'b0;
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if(&RW & Atomic[1]) begin // amo write
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if(&RW & Atomic[1]) begin // amo write
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PreSelAdr = 2'b01;
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PreSelAdr = 2'b01;
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if(CPUBusy) begin
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if(CPUBusy) begin
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@ -272,11 +265,9 @@ module cachefsm
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if(~`REPLAY) save = 1'b1;
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if(~`REPLAY) save = 1'b1;
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end
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end
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else begin
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else begin
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LRUWriteEn = 1'b1;
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NextState = STATE_READY;
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NextState = STATE_READY;
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end
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end
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end else begin
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end else begin
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LRUWriteEn = 1'b1;
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if(CPUBusy) begin
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if(CPUBusy) begin
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NextState = STATE_CPU_BUSY;
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NextState = STATE_CPU_BUSY;
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if(`REPLAY) PreSelAdr = 2'b01;
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if(`REPLAY) PreSelAdr = 2'b01;
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@ -290,7 +281,6 @@ module cachefsm
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STATE_MISS_WRITE_WORD: begin
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STATE_MISS_WRITE_WORD: begin
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PreSelAdr = 2'b01;
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PreSelAdr = 2'b01;
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LRUWriteEn = 1'b1;
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if(CPUBusy) begin
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if(CPUBusy) begin
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NextState = STATE_CPU_BUSY;
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NextState = STATE_CPU_BUSY;
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if(`REPLAY) PreSelAdr = 2'b01;
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if(`REPLAY) PreSelAdr = 2'b01;
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@ -325,27 +315,25 @@ module cachefsm
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STATE_CPU_BUSY_FINISH_AMO: begin
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STATE_CPU_BUSY_FINISH_AMO: begin
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PreSelAdr = 2'b01;
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PreSelAdr = 2'b01;
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LRUWriteEn = 1'b0;
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restore = 1'b1;
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restore = 1'b1;
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if(CPUBusy) begin
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if(CPUBusy) begin
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NextState = STATE_CPU_BUSY_FINISH_AMO;
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NextState = STATE_CPU_BUSY_FINISH_AMO;
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end
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end
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else begin
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else begin
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LRUWriteEn = 1'b1;
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NextState = STATE_READY;
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NextState = STATE_READY;
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end
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end
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end
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end
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STATE_FLUSH: begin
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STATE_FLUSH: begin
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// intialize flush counters
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// intialize flush counters
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SelFlush = 1'b1;
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//SelFlush = 1'b1;
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PreSelAdr = 2'b10;
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PreSelAdr = 2'b10;
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NextState = STATE_FLUSH_CHECK;
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NextState = STATE_FLUSH_CHECK;
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end
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end
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STATE_FLUSH_CHECK: begin
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STATE_FLUSH_CHECK: begin
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PreSelAdr = 2'b10;
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PreSelAdr = 2'b10;
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SelFlush = 1'b1;
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//SelFlush = 1'b1;
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if(VictimDirty) begin
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if(VictimDirty) begin
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NextState = STATE_FLUSH_WRITE_BACK;
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NextState = STATE_FLUSH_WRITE_BACK;
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FlushWayCntEn = 1'b0;
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FlushWayCntEn = 1'b0;
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@ -356,8 +344,6 @@ module cachefsm
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FlushWayCntEn = 1'b0;
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FlushWayCntEn = 1'b0;
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end else if(FlushWayFlag) begin
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end else if(FlushWayFlag) begin
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NextState = STATE_FLUSH_INCR;
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NextState = STATE_FLUSH_INCR;
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FlushAdrCntEn = 1'b1;
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FlushWayCntEn = 1'b1;
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FlushWayCntEn = 1'b1;
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end else begin
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end else begin
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FlushWayCntEn = 1'b1;
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FlushWayCntEn = 1'b1;
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@ -367,14 +353,14 @@ module cachefsm
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STATE_FLUSH_INCR: begin
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STATE_FLUSH_INCR: begin
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PreSelAdr = 2'b10;
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PreSelAdr = 2'b10;
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SelFlush = 1'b1;
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//SelFlush = 1'b1;
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FlushWayCntRst = 1'b1;
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FlushWayCntRst = 1'b1;
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NextState = STATE_FLUSH_CHECK;
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NextState = STATE_FLUSH_CHECK;
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end
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end
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STATE_FLUSH_WRITE_BACK: begin
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STATE_FLUSH_WRITE_BACK: begin
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PreSelAdr = 2'b10;
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PreSelAdr = 2'b10;
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SelFlush = 1'b1;
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//SelFlush = 1'b1;
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if(CacheBusAck) begin
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if(CacheBusAck) begin
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NextState = STATE_FLUSH_CLEAR_DIRTY;
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NextState = STATE_FLUSH_CLEAR_DIRTY;
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end else begin
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end else begin
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@ -384,7 +370,7 @@ module cachefsm
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STATE_FLUSH_CLEAR_DIRTY: begin
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STATE_FLUSH_CLEAR_DIRTY: begin
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VDWriteEnable = 1'b1;
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VDWriteEnable = 1'b1;
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SelFlush = 1'b1;
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//SelFlush = 1'b1;
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PreSelAdr = 2'b10;
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PreSelAdr = 2'b10;
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FlushWayCntEn = 1'b0;
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FlushWayCntEn = 1'b0;
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if(FlushAdrFlag & FlushWayFlag) begin
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if(FlushAdrFlag & FlushWayFlag) begin
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@ -392,7 +378,6 @@ module cachefsm
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PreSelAdr = 2'b00;
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PreSelAdr = 2'b00;
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end else if (FlushWayFlag) begin
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end else if (FlushWayFlag) begin
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NextState = STATE_FLUSH_INCR;
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NextState = STATE_FLUSH_INCR;
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FlushAdrCntEn = 1'b1;
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FlushWayCntEn = 1'b1;
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FlushWayCntEn = 1'b1;
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end else begin
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end else begin
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@ -434,6 +419,15 @@ module cachefsm
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(CurrState == STATE_MISS_WRITE_WORD);
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(CurrState == STATE_MISS_WRITE_WORD);
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assign SRAMLineWriteEnable = (CurrState == STATE_MISS_WRITE_CACHE_LINE);
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assign SRAMLineWriteEnable = (CurrState == STATE_MISS_WRITE_CACHE_LINE);
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assign SelEvict = (CurrState == STATE_MISS_EVICT_DIRTY);
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assign SelEvict = (CurrState == STATE_MISS_EVICT_DIRTY);
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assign LRUWriteEn = (CurrState == STATE_READY & (DoAMOHit | DoReadHit | DoWriteHit)) |
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(CurrState == STATE_MISS_READ_WORD_DELAY) |
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(CurrState == STATE_MISS_WRITE_WORD);
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assign SelFlush = (CurrState == STATE_FLUSH) | (CurrState == STATE_FLUSH_CHECK) |
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(CurrState == STATE_FLUSH_INCR) | (CurrState == STATE_FLUSH_WRITE_BACK) |
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(CurrState == STATE_FLUSH_CLEAR_DIRTY);
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assign FlushAdrCntEn = (CurrState == STATE_FLUSH_CHECK & VictimDirty & FlushWayFlag & ~FlushAdrFlag) |
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(CurrState == STATE_FLUSH_CLEAR_DIRTY & FlushWayFlag & ~FlushAdrFlag);
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endmodule // cachefsm
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endmodule // cachefsm
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