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Cache fsm simplifications.

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This commit is contained in:
Ross Thompson 2022-02-11 15:16:45 -06:00
parent e2e0a4f595
commit 52894a7a4f
1 changed files with 7 additions and 8 deletions
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15
pipelined/src/cache/cachefsm.sv vendored
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@ -82,7 +82,7 @@ module cachefsm
logic resetDelay; logic resetDelay;
logic AMO; logic AMO;
logic DoAMO, DoRead, DoWrite, DoFlush; logic DoAMO, DoRead, DoWrite, DoFlush;
logic DoAMOHit, DoReadHit, DoWriteHit, DoAnyHit; logic DoAMOHit, DoReadHit, DoWriteHit, DoAnyUpdateHit, DoAnyHit;
logic DoAMOMiss, DoReadMiss, DoWriteMiss, DoAnyMiss; logic DoAMOMiss, DoReadMiss, DoWriteMiss, DoAnyMiss;
logic FlushFlag, FlushWayAndNotAdrFlag; logic FlushFlag, FlushWayAndNotAdrFlag;
@ -124,8 +124,9 @@ module cachefsm
assign DoWriteHit = DoWrite & CacheHit; assign DoWriteHit = DoWrite & CacheHit;
assign DoWriteMiss = DoWrite & ~CacheHit; assign DoWriteMiss = DoWrite & ~CacheHit;
assign DoAnyMiss = DoAMOMiss | DoReadMiss | DoWriteMiss; assign DoAnyMiss = (DoAMO | DoRead | DoWrite) & ~CacheHit;
assign DoAnyHit = DoAMOHit | DoReadHit | DoWriteHit; assign DoAnyUpdateHit = DoAMOHit | DoWriteHit;
assign DoAnyHit = DoAnyUpdateHit | DoReadHit;
assign FlushFlag = FlushAdrFlag & FlushWayFlag; assign FlushFlag = FlushAdrFlag & FlushWayFlag;
// outputs for the performance counters. // outputs for the performance counters.
@ -147,10 +148,8 @@ module cachefsm
case (CurrState) case (CurrState)
STATE_READY: if(IgnoreRequest) NextState = STATE_READY; STATE_READY: if(IgnoreRequest) NextState = STATE_READY;
else if(DoFlush) NextState = STATE_FLUSH; else if(DoFlush) NextState = STATE_FLUSH;
else if(DoAMOHit & CPUBusy) NextState = STATE_CPU_BUSY; // change else if(DoAnyHit & CPUBusy) NextState = STATE_CPU_BUSY;
else if(DoReadHit & CPUBusy) NextState = STATE_CPU_BUSY; else if(DoAnyMiss) NextState = STATE_MISS_FETCH_WDV; // change
else if(DoWriteHit & CPUBusy) NextState = STATE_CPU_BUSY;
else if(DoReadMiss | DoWriteMiss | DoAMOMiss) NextState = STATE_MISS_FETCH_WDV; // change
else NextState = STATE_READY; else NextState = STATE_READY;
STATE_MISS_FETCH_WDV: if (CacheBusAck) NextState = STATE_MISS_FETCH_DONE; STATE_MISS_FETCH_WDV: if (CacheBusAck) NextState = STATE_MISS_FETCH_DONE;
else NextState = STATE_MISS_FETCH_WDV; else NextState = STATE_MISS_FETCH_WDV;
@ -205,7 +204,7 @@ module cachefsm
(CurrState == STATE_MISS_WRITE_WORD); (CurrState == STATE_MISS_WRITE_WORD);
assign ClearDirty = (CurrState == STATE_MISS_WRITE_CACHE_LINE) | assign ClearDirty = (CurrState == STATE_MISS_WRITE_CACHE_LINE) |
(CurrState == STATE_FLUSH_CLEAR_DIRTY); (CurrState == STATE_FLUSH_CLEAR_DIRTY);
assign FSMWordWriteEn = (CurrState == STATE_READY & (DoAMOHit | DoWriteHit)) | assign FSMWordWriteEn = (CurrState == STATE_READY & (DoAnyUpdateHit)) |
(CurrState == STATE_MISS_READ_WORD_DELAY & AMO) | (CurrState == STATE_MISS_READ_WORD_DELAY & AMO) |
(CurrState == STATE_MISS_WRITE_WORD); (CurrState == STATE_MISS_WRITE_WORD);
assign FSMLineWriteEn = (CurrState == STATE_MISS_WRITE_CACHE_LINE); assign FSMLineWriteEn = (CurrState == STATE_MISS_WRITE_CACHE_LINE);