small signal cleanup

pipelined/src/fpu/fdivsqrt/fdivsqrt.sv

@@ -67,7 +67,7 @@ module fdivsqrt(
 
   fdivsqrtpreproc fdivsqrtpreproc(
     .clk, .DivStartE, .Xm(XmE), .QeM, .Xe(XeE), .Fmt(FmtE), .Ye(YeE), 
-    .Sqrt(SqrtE), .Int(MDUE), .Ym(YmE), .XZero(XZeroE), .X, .Dpreproc, 
+    .Sqrt(SqrtE), .Ym(YmE), .XZero(XZeroE), .X, .Dpreproc, 
     .ForwardedSrcAE, .ForwardedSrcBE, .Funct3E, .Funct3M, .MDUE, .W64E);
   fdivsqrtfsm fdivsqrtfsm(
     .clk, .reset, .FmtE, .XsE, .SqrtE, 

pipelined/src/fpu/fdivsqrt/fdivsqrtiter.sv

@@ -50,7 +50,7 @@ module fdivsqrtiter(
 //QLEN = 1.(number of bits created for division)
 // N is NF+1 or XLEN
 // WC/WS is dependent on D so 4.N-1 ie N+3 bits or N+2:0 + one more bit in fraction for possible sqrt right shift
-// D is 1.N-1, but the msb is always 1 so 0.N-1 or N-1 bits or N-1:0
+// D is 1.N-1, but the msb is always 1 so 0.N-1 or N-1 bits or N-2:0
 // Dsel should match WC/WS so 4.N-1 ie N+3 bits or N+2:0
 // U/UM should be 1.b so b+1 bits or b:0
 // C needs to be the lenght of the final fraction 0.b so b or b-1:0

pipelined/src/fpu/fdivsqrt/fdivsqrtpreproc.sv

@@ -37,7 +37,6 @@ module fdivsqrtpreproc (
   input  logic [`NE-1:0] Xe, Ye,
   input  logic [`FMTBITS-1:0] Fmt,
   input  logic Sqrt,
-  input  logic Int,
   input  logic XZero,
   input  logic [`XLEN-1:0] ForwardedSrcAE, ForwardedSrcBE, // *** these are the src outputs before the mux choosing between them and PCE to put in srcA/B
 	input  logic [2:0] 	Funct3E, Funct3M,