forked from Github_Repos/cvw
Fixed exponent verification, added sign module and added sign tests
This commit is contained in:
cturek
parent
f35450207f
commit
51debfa186
@ -1 +1 @@
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Subproject commit be67c99bd461742aa1c100bcc0732657faae2230
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Subproject commit 307c77b26e070ae85ffea665ad9b642b40e33c86
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@ -21,7 +21,7 @@
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/* Prototypes */
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void output(FILE *fptr, int e1, double a, int e2, double b, int r_exp, double r_mantissa);
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void output(FILE *fptr, int signa, int e1, double a, int signb, int e2, double b, int r_sign, int r_exp, double r_mantissa);
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void printhex(FILE *fptr, double x);
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double random_input(void);
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double random_input_e(void);
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@ -35,8 +35,8 @@ void main(void)
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// a & b are mantissas
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// r_mantissa is result of mantissa divsion
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// r_exp is result of exponent division
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double a, b, r_mantissa, r_exp;
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int e1, e2;
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double a, b, r_mantissa, r_exp, r_sign;
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int e1, e2, signa, signb;
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double mantissa[ENTRIES] = {1, 1.5, 1.25, 1.125, 1.0625,
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1.75, 1.875, 1.99999,
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1.1, 1.2, 1.01, 1.001, 1.0001,
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@ -53,12 +53,15 @@ void main(void)
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for (i=0; i<ENTRIES; i++) {
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b = mantissa[i];
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e2 = exponent[i] + bias;
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signb = i%2;
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for (j=0; j<ENTRIES; j++) {
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a = mantissa[j];
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e1 = exponent[j] + bias;
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signa = j%2;
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r_mantissa = a/b;
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r_exp = e1 - e2 + bias;
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output(fptr, e1, a, e2, b, r_exp, r_mantissa);
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r_sign = (i+j)%2;
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output(fptr, signa, e1, a, signb, e2, b, r_sign, r_exp, r_mantissa);
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}
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}
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@ -77,17 +80,17 @@ void main(void)
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/* Functions */
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void output(FILE *fptr, int e1, double a, int e2, double b, int r_exp, double r_mantissa)
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void output(FILE *fptr, int signa, int e1, double a, int signb, int e2, double b, int r_sign, int r_exp, double r_mantissa)
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{
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fprintf(fptr, "%03x", e1);
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fprintf(fptr, "%03x", e1|(signa<<11));
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//printhex(fptr, e1, exp);
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printhex(fptr, a);
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fprintf(fptr, "_");
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fprintf(fptr, "%03x", e2);
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fprintf(fptr, "%03x", e2|(signb<<11));
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//printhex(fptr, e2, exp);
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printhex(fptr, b);
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fprintf(fptr, "_");
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fprintf(fptr, "%03x", r_exp);
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fprintf(fptr, "%03x", r_exp|(r_sign<<11));
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//printhex(fptr, r_exp, exp);
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printhex(fptr, r_mantissa);
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fprintf(fptr, "\n");
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@ -37,6 +37,7 @@ module srt #(parameter Nf=52) (
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input logic Flush, // *** multiple pipe stages
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// Floating Point Inputs
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// later add exponents, signs, special cases
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input logic XSign, YSign,
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input logic [`NE-1:0] XExp, YExp,
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input logic [Nf-1:0] SrcXFrac, SrcYFrac,
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input logic [`XLEN-1:0] SrcA, SrcB,
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@ -45,12 +46,15 @@ module srt #(parameter Nf=52) (
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input logic Signed, // Interpret integers as signed 2's complement
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input logic Int, // Choose integer inputss
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input logic Sqrt, // perform square root, not divide
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output logic rsign,
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output logic [Nf-1:0] Quot, Rem, // *** later handle integers
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output logic [`NE-1:0] rExp,
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output logic [3:0] Flags
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);
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logic qp, qz, qm; // quotient is +1, 0, or -1
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logic [`NE-1:0] calcExp;
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logic calcSign;
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logic [Nf-1:0] X, Dpreproc;
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logic [Nf+3:0] WS, WSA, WSN, WC, WCA, WCN, D, Db, Dsel;
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logic [Nf+2:0] rp, rm;
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@ -72,6 +76,8 @@ module srt #(parameter Nf=52) (
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// Accumulate quotient digits in a shift register
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qsel #(Nf) qsel(WS[55:52], WC[55:52], qp, qz, qm);
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qacc #(Nf+3) qacc(clk, Start, qp, qz, qm, rp, rm);
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flopen #(`NE) expflop(clk, Start, calcExp, rExp);
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flopen #(1) signflop(clk, Start, calcSign, rsign);
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// Divisor Selection logic
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inv dinv(D, Db);
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@ -80,7 +86,9 @@ module srt #(parameter Nf=52) (
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// Partial Product Generation
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csa csa(WS, WC, Dsel, qp, WSA, WCA);
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expcalc expcalc(.XExp, .YExp, .rExp);
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expcalc expcalc(.XExp, .YExp, .calcExp);
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signcalc signcalc(.XSign, .YSign, .calcSign);
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srtpostproc postproc(rp, rm, Quot);
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endmodule
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@ -258,10 +266,23 @@ endmodule
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module expcalc(
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input logic [`NE-1:0] XExp, YExp,
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output logic [`NE-1:0] rExp
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output logic [`NE-1:0] calcExp
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);
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assign rExp = XExp - YExp + `BIAS;
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assign calcExp = XExp - YExp + `BIAS;
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endmodule
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//////////////
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// signcalc //
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//////////////
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module signcalc(
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input logic XSign, YSign,
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output logic calcSign
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);
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assign calcSign = XSign ^ YSign;
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endmodule
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@ -40,8 +40,10 @@ module testbench;
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logic clk;
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logic req;
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logic done;
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logic [62:0] a;
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logic [62:0] b;
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logic [63:0] a, b;
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logic [51:0] afrac, bfrac;
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logic [10:0] aExp, bExp;
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logic asign, bsign;
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logic [51:0] r;
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logic [54:0] rp, rm; // positive quotient digits
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@ -49,23 +51,25 @@ module testbench;
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parameter MEM_SIZE = 40000;
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parameter MEM_WIDTH = 64+64+64;
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`define memr 62:0
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`define memb 126:64
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`define mema 190:128
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`define memr 63:0
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`define memb 127:64
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`define mema 191:128
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// Test logicisters
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logic [MEM_WIDTH-1:0] Tests [0:MEM_SIZE]; // Space for input file
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logic [MEM_WIDTH-1:0] Vec; // Verilog doesn't allow direct access to a
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// bit field of an array
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logic [62:0] correctr, nextr, diffn, diffp;
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logic [63:0] correctr, nextr, diffn, diffp;
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logic [10:0] rExp;
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logic rsign;
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integer testnum, errors;
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// Divider
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srt #(52) srt(.clk, .Start(req),
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.Stall(1'b0), .Flush(1'b0),
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.XExp(a[62:52]), .YExp(b[62:52]), .rExp,
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.SrcXFrac(a[51:0]), .SrcYFrac(b[51:0]),
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.XExp(aExp), .YExp(bExp), .rExp,
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.XSign(asign), .YSign(bsign), .rsign,
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.SrcXFrac(afrac), .SrcYFrac(bfrac),
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.SrcA('0), .SrcB('0), .Fmt(2'b00),
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.W64(1'b0), .Signed(1'b0), .Int(1'b0), .Sqrt(1'b0),
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.Quot(r), .Rem(), .Flags());
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@ -90,7 +94,9 @@ module testbench;
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$readmemh ("testvectors", Tests);
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Vec = Tests[testnum];
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a = Vec[`mema];
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{asign, aExp, afrac} = a;
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b = Vec[`memb];
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{bsign, bExp, bfrac} = b;
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nextr = Vec[`memr];
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req <= #5 1;
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end
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@ -104,14 +110,14 @@ module testbench;
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req <= #5 1;
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diffp = correctr[51:0] - r;
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diffn = r - correctr[51:0];
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if ((rExp === correctr[62:52]) | ($signed(diffn) > 1) | ($signed(diffp) > 1)) // check if accurate to 1 ulp
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if ((rsign !== correctr[63]) | (rExp !== correctr[62:52]) | ($signed(diffn) > 1) | ($signed(diffp) > 1)) // check if accurate to 1 ulp
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begin
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errors = errors+1;
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$display("result was %h_%h, should be %h %h %h\n", rExp, r, correctr, diffn, diffp);
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$display("failed\n");
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$stop;
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end
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if (a === 52'hxxxxxxxxxxxxx)
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if (afrac === 52'hxxxxxxxxxxxxx)
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begin
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$display("%d Tests completed successfully", testnum);
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$stop;
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@ -125,7 +131,9 @@ module testbench;
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Vec = Tests[testnum];
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$display("a = %h b = %h",a,b);
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a = Vec[`mema];
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{asign, aExp, afrac} = a;
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b = Vec[`memb];
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{bsign, bExp, bfrac} = b;
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nextr = Vec[`memr];
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end
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end
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@ -1,289 +1,289 @@
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4000000000000000_4000000000000000_3ff0000000000000
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4018000000000000_4000000000000000_4008000000000000
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c018000000000000_4000000000000000_c008000000000000
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c032000000000000_4000000000000000_c022000000000000
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c093333333333333_4000000000000000_c083333333333333
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||||
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|
||||
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|
||||
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|
||||
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||||
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||||
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||||
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|
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||||
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|
||||
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|
||||
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|
||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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|
||||
c0f999999999999a_c018000000000000_40d1111111111111
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||||
410c71c71c71c71c_c018000000000000_c0e2f684bda12f68
|
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4000000000000000_4024000000000000_3fd999999999999a
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||||
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|
||||
c018000000000000_4024000000000000_bfe3333333333333
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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|
||||
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|
||||
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|
||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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|
||||
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||||
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|
||||
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||||
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|
||||
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|
||||
c07ffff583a53b8e_4041000000000000_c02e1e143faa9268
|
||||
408199999999999a_4041000000000000_4030909090909091
|
||||
4093333333333333_4041000000000000_4042121212121212
|
||||
c093333333333333_4041000000000000_c042121212121212
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4024000000000000_40dd1745d1745d17_3f46000000000000
|
||||
4032000000000000_40dd1745d1745d17_3f53cccccccccccd
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4041000000000000_40dd1745d1745d17_3f62b33333333333
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||||
405c000000000000_40dd1745d1745d17_3f7ecccccccccccd
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406e000000000000_40dd1745d1745d17_3f80800000000000
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407ffff583a53b8e_40dd1745d1745d17_3f919993d5347a5b
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40a028f5c28f5c29_40dd1745d1745d17_3fc1c6a7ef9db22d
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40b004189374bc6a_40dd1745d1745d17_3fd19e1b089a0275
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40c00068db8bac71_40dd1745d1745d17_3fe19a0cf1800a7c
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40dd1745d1745d17_40dd1745d1745d17_3ff0000000000000
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40e5555555555555_40dd1745d1745d17_4007777777777777
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4000000000000000_c0dd1745d1745d17_bf2199999999999a
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||||
c018000000000000_c0dd1745d1745d17_3f3a666666666667
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4024000000000000_c0dd1745d1745d17_bf46000000000000
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||||
c032000000000000_c0dd1745d1745d17_3f53cccccccccccd
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4041000000000000_c0dd1745d1745d17_bf62b33333333333
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||||
c05c000000000000_c0dd1745d1745d17_3f7ecccccccccccd
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c07ffff583a53b8e_c0dd1745d1745d17_3f919993d5347a5b
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408199999999999a_c0dd1745d1745d17_bfa35c28f5c28f5d
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c093333333333333_c0dd1745d1745d17_3fb51eb851eb851f
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40a028f5c28f5c29_c0dd1745d1745d17_bfc1c6a7ef9db22d
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c0b004189374bc6a_c0dd1745d1745d17_3fd19e1b089a0275
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40c00068db8bac71_c0dd1745d1745d17_bfe19a0cf1800a7c
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c0dd1745d1745d17_c0dd1745d1745d17_3ff0000000000000
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40e5555555555555_c0dd1745d1745d17_c007777777777777
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c0f999999999999a_c0dd1745d1745d17_401c28f5c28f5c2a
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410c71c71c71c71c_c0dd1745d1745d17_c02f49f49f49f49f
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4000000000000000_40e5555555555555_3f18000000000000
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4018000000000000_40e5555555555555_3f22000000000000
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c018000000000000_40e5555555555555_bf22000000000000
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4024000000000000_40e5555555555555_3f3e000000000000
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4032000000000000_40e5555555555555_3f4b000000000000
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c032000000000000_40e5555555555555_bf4b000000000000
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4041000000000000_40e5555555555555_3f59800000000000
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405c000000000000_40e5555555555555_3f65000000000000
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c05c000000000000_40e5555555555555_bf65000000000000
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406e000000000000_40e5555555555555_3f76800000000000
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407ffff583a53b8e_40e5555555555555_3f87fff822bbecab
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c07ffff583a53b8e_40e5555555555555_bf87fff822bbecab
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408199999999999a_40e5555555555555_3f9a666666666667
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||||
4093333333333333_40e5555555555555_3faccccccccccccd
|
||||
c093333333333333_40e5555555555555_bfaccccccccccccd
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||||
40a028f5c28f5c29_40e5555555555555_3fb83d70a3d70a3e
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40b004189374bc6a_40e5555555555555_3fc80624dd2f1a9f
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c0b004189374bc6a_40e5555555555555_bfc80624dd2f1a9f
|
||||
40c00068db8bac71_40e5555555555555_3fd8009d495182aa
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40dd1745d1745d17_40e5555555555555_3fe5d1745d1745d2
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c0dd1745d1745d17_40e5555555555555_bfe5d1745d1745d2
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||||
40e5555555555555_40e5555555555555_3ff0000000000000
|
||||
40f999999999999a_40e5555555555555_4003333333333334
|
||||
c0f999999999999a_40e5555555555555_c003333333333334
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||||
410c71c71c71c71c_40e5555555555555_4015555555555555
|
||||
4000000000000000_40f999999999999a_3f04000000000000
|
||||
4018000000000000_40f999999999999a_3f1e000000000000
|
||||
4024000000000000_40f999999999999a_3f29000000000000
|
||||
4032000000000000_40f999999999999a_3f36800000000000
|
||||
4041000000000000_40f999999999999a_3f45400000000000
|
||||
405c000000000000_40f999999999999a_3f51800000000000
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406e000000000000_40f999999999999a_3f62c00000000000
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407ffff583a53b8e_40f999999999999a_3f73fff972474538
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408199999999999a_40f999999999999a_3f86000000000000
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4093333333333333_40f999999999999a_3f97ffffffffffff
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40a028f5c28f5c29_40f999999999999a_3fa4333333333333
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40b004189374bc6a_40f999999999999a_3fb4051eb851eb84
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40c00068db8bac71_40f999999999999a_3fc40083126e978d
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||||
40dd1745d1745d17_40f999999999999a_3fd22e8ba2e8ba2e
|
||||
40e5555555555555_40f999999999999a_3feaaaaaaaaaaaaa
|
||||
40f999999999999a_40f999999999999a_3ff0000000000000
|
||||
410c71c71c71c71c_40f999999999999a_4001c71c71c71c71
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||||
4000000000000000_c0f999999999999a_bf04000000000000
|
||||
c018000000000000_c0f999999999999a_3f1e000000000000
|
||||
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||||
c032000000000000_c0f999999999999a_3f36800000000000
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||||
4041000000000000_c0f999999999999a_bf45400000000000
|
||||
c05c000000000000_c0f999999999999a_3f51800000000000
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406e000000000000_c0f999999999999a_bf62c00000000000
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c07ffff583a53b8e_c0f999999999999a_3f73fff972474538
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c093333333333333_c0f999999999999a_3f97ffffffffffff
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c0b004189374bc6a_c0f999999999999a_3fb4051eb851eb84
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c0dd1745d1745d17_c0f999999999999a_3fd22e8ba2e8ba2e
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40e5555555555555_c0f999999999999a_bfeaaaaaaaaaaaaa
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c0f999999999999a_c0f999999999999a_3ff0000000000000
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||||
410c71c71c71c71c_c0f999999999999a_c001c71c71c71c71
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||||
4000000000000000_410c71c71c71c71c_3ef2000000000000
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||||
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c018000000000000_410c71c71c71c71c_bf0b000000000000
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c032000000000000_410c71c71c71c71c_bf24400000000000
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4041000000000000_410c71c71c71c71c_3f33200000000000
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405c000000000000_410c71c71c71c71c_3f4f800000000000
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c05c000000000000_410c71c71c71c71c_bf4f800000000000
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||||
406e000000000000_410c71c71c71c71c_3f50e00000000000
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c07ffff583a53b8e_410c71c71c71c71c_bf61fffa1a0cf180
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408199999999999a_410c71c71c71c71c_3f73ccccccccccce
|
||||
4093333333333333_410c71c71c71c71c_3f8599999999999a
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||||
c093333333333333_410c71c71c71c71c_bf8599999999999a
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40b004189374bc6a_410c71c71c71c71c_3fa2049ba5e353f8
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||||
c0b004189374bc6a_410c71c71c71c71c_bfa2049ba5e353f8
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40c00068db8bac71_410c71c71c71c71c_3fb20075f6fd21ff
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||||
40dd1745d1745d17_410c71c71c71c71c_3fc05d1745d1745d
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||||
c0dd1745d1745d17_410c71c71c71c71c_bfc05d1745d1745d
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||||
40e5555555555555_410c71c71c71c71c_3fd8000000000000
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||||
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|
||||
c0f999999999999a_410c71c71c71c71c_bfecccccccccccce
|
||||
410c71c71c71c71c_410c71c71c71c71c_3ff0000000000000
|
||||
Loading…
Reference in New Issue
Block a user