forked from Github_Repos/cvw
start to add buildroot testbench
This still uses testbench-busybear.sv I think it might be time to finally rename nearly 'busybear' thing to 'linux'
This commit is contained in:
Noah Boorstin
parent
b533d17ed8
commit
4f97e9e761
1024
wally-pipelined/config/buildroot/BTBPredictor.txt
Normal file
1024
wally-pipelined/config/buildroot/BTBPredictor.txt
Normal file
File diff suppressed because it is too large
Load Diff
1024
wally-pipelined/config/buildroot/twoBitPredictor.txt
Normal file
1024
wally-pipelined/config/buildroot/twoBitPredictor.txt
Normal file
File diff suppressed because it is too large
Load Diff
107
wally-pipelined/config/buildroot/wally-config.vh
Normal file
107
wally-pipelined/config/buildroot/wally-config.vh
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@ -0,0 +1,107 @@
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//////////////////////////////////////////
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// busybear-config.vh
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//
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// Written: David_Harris@hmc.edu 4 January 2021
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// Modified:
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//
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// Purpose: Specify which features are configured
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// Macros to determine which modes are supported based on MISA
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//
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// A component of the Wally configurable RISC-V project.
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//
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// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
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//
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// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
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// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy,
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// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software
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// is furnished to do so, subject to the following conditions:
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//
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// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
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//
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// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
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||||
// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
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// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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///////////////////////////////////////////
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`define BUSYBEAR
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`define BUSYBEAR_FIX_READ {'h10000005}
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`define BUSYBEAR_TEST_VECTORS "/courses/e190ax/buildroot_boot/"
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// RV32 or RV64: XLEN = 32 or 64
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`define XLEN 64
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`define MISA (32'h0014112D)
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`define A_SUPPORTED ((`MISA >> 0) % 2 == 1)
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`define C_SUPPORTED ((`MISA >> 2) % 2 == 1)
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`define D_SUPPORTED ((`MISA >> 3) % 2 == 1)
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`define F_SUPPORTED ((`MISA >> 5) % 2 == 1)
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`define M_SUPPORTED ((`MISA >> 12) % 2 == 1)
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`define S_SUPPORTED ((`MISA >> 18) % 2 == 1)
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`define U_SUPPORTED ((`MISA >> 20) % 2 == 1)
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`define ZCSR_SUPPORTED 1
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`define ZCOUNTERS_SUPPORTED 1
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`define COUNTERS 31
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// N-mode user-level interrupts are depricated per Andrew Waterman 1/13/21
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//`define N_SUPPORTED ((MISA >> 13) % 2 == 1)
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`define N_SUPPORTED 0
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`define M_MODE (2'b11)
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`define S_MODE (2'b01)
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`define U_MODE (2'b00)
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// Microarchitectural Features
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`define UARCH_PIPELINED 1
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`define UARCH_SUPERSCALR 0
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`define UARCH_SINGLECYCLE 0
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`define MEM_DCACHE 0
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`define MEM_DTIM 1
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`define MEM_ICACHE 0
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`define MEM_VIRTMEM 0
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`define VECTORED_INTERRUPTS_SUPPORTED 1 // Domenico Ottolia 4/15: Support for vectored interrupts in _tvec csrs. Just implemented in src/privileged/trap.sv around line 75. Pretty sure this should be 1.
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// Address space
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`define RESET_VECTOR 64'h0000000000001000
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// Peripheral Addresses
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// Peripheral memory space extends from BASE to BASE+RANGE
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// Range should be a thermometer code with 0's in the upper bits and 1s in the lower bits
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`define BOOTTIMBASE 32'h00000000 //only needs to go from 0x1000 to 0x2FFF, extending to a power of 2
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`define BOOTTIMRANGE 32'h00003FFF
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`define CLINTBASE 32'h02000000
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`define CLINTRANGE 32'h0000FFFF
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`define PLICBASE 32'h0C000000
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`define PLICRANGE 32'h03FFFFFF
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`define UARTBASE 32'h10000000
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`define UARTRANGE 32'h00000007
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`define VBD0BASE 32'h10001000
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`define VBD0RANGE 32'h000001FF
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// differing from Imperas' OVPSim by not having a VND0
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`define GPIOBASE 32'h20000000
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`define GPIORANGE 32'h000000FF
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`define TIMBASE 32'h80000000
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`define TIMRANGE 32'h07FFFFFF
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// Bus Interface width
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`define AHBW 64
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// Test modes
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// Tie GPIO outputs back to inputs
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`define GPIO_LOOPBACK_TEST 0
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// Busybear special CSR config to match OVPSim
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`define OVPSIM_CSR_CONFIG 1
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// Hardware configuration
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`define UART_PRESCALE 1
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// Interrupt configuration
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`define PLIC_NUM_SRC 53
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`define PLIC_UART_ID 4
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/* verilator lint_off STMTDLY */
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/* verilator lint_off WIDTH */
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`define TWO_BIT_PRELOAD "../config/busybear/twoBitPredictor.txt"
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`define BTB_PRELOAD "../config/busybear/BTBPredictor.txt"
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`define BPTYPE "BPGSHARE" // BPGLOBAL or BPTWOBIT or BPGSHARE
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33
wally-pipelined/config/buildroot/wally-constants.vh
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33
wally-pipelined/config/buildroot/wally-constants.vh
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@ -0,0 +1,33 @@
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//////////////////////////////////////////
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// wally-constants.vh
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//
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// Written: tfleming@hmc.edu 4 March 2021
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// Modified:
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//
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// Purpose: Specify certain constants defined in the RISC-V 64-bit architecture.
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// These macros should not be changed, except in the event of an
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// update to the architecture or particularly special circumstances.
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//
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// A component of the Wally configurable RISC-V project.
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//
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// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
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//
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// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
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// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy,
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// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software
|
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// is furnished to do so, subject to the following conditions:
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//
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// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
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//
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// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
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// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
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// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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///////////////////////////////////////////
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// Virtual Memory Constants (sv39)
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`define VPN_SEGMENT_BITS 9
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`define VPN_BITS 27
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`define PPN_BITS 44
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`define PPN_HIGH_SEGMENT_BITS 26
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`define PA_BITS 56
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@ -26,6 +26,7 @@
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`define BUSYBEAR
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`define BUSYBEAR_FIX_READ {'h10000005}
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`define BUSYBEAR_TEST_VECTORS "/courses/e190ax/busybear_boot_new/"
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// RV32 or RV64: XLEN = 32 or 64
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`define XLEN 64
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1
wally-pipelined/regression/sim-buildroot
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1
wally-pipelined/regression/sim-buildroot
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vsim -do wally-buildroot.do
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3
wally-pipelined/regression/sim-buildroot-batch
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3
wally-pipelined/regression/sim-buildroot-batch
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vsim -c <<!
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do wally-buildroot-batch.do
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!
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39
wally-pipelined/regression/wally-buildroot-batch.do
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39
wally-pipelined/regression/wally-buildroot-batch.do
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@ -0,0 +1,39 @@
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# wally-pipelined.do
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#
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# Modification by Oklahoma State University & Harvey Mudd College
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# Use with testbench_busybear
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# James Stine, 2008; David Harris 2021
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# Go Cowboys!!!!!!
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#
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# Takes 1:10 to run RV64IC tests using gui
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# Use this wally-pipelined.do file to run this example.
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# Either bring up ModelSim and type the following at the "ModelSim>" prompt:
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# do wally-pipelined.do
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# or, to run from a shell, type the following at the shell prompt:
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# vsim -do wally-pipelined.do -c
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# (omit the "-c" to see the GUI while running from the shell)
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onbreak {resume}
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# create library
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if [file exists work-buildroot] {
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vdel -all -lib work-buildroot
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}
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vlib work-buildroot
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# compile source files
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# suppress spurious warnngs about
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# "Extra checking for conflicts with always_comb done at vopt time"
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# because vsim will run vopt
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vlog +incdir+../config/buildroot ../testbench/testbench-busybear.sv ../src/*/*.sv -suppress 2583
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# start and run simulation
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# remove +acc flag for faster sim during regressions if there is no need to access internal signals
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vopt work.testbench_busybear -o workopt
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vsim workopt -suppress 8852,12070
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run -all
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quit
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166
wally-pipelined/regression/wally-buildroot.do
Normal file
166
wally-pipelined/regression/wally-buildroot.do
Normal file
@ -0,0 +1,166 @@
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# wally-pipelined.do
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#
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# Modification by Oklahoma State University & Harvey Mudd College
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# Use with testbench_busybear
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# James Stine, 2008; David Harris 2021
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# Go Cowboys!!!!!!
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#
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# Takes 1:10 to run RV64IC tests using gui
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# Use this wally-pipelined.do file to run this example.
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# Either bring up ModelSim and type the following at the "ModelSim>" prompt:
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# do wally-pipelined.do
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# or, to run from a shell, type the following at the shell prompt:
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# vsim -do wally-pipelined.do -c
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# (omit the "-c" to see the GUI while running from the shell)
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onbreak {resume}
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# create library
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if [file exists work-buildroot] {
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vdel -all -lib work-buildroot
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}
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vlib work-buildroot
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# compile source files
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# suppress spurious warnngs about
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# "Extra checking for conflicts with always_comb done at vopt time"
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# because vsim will run vopt
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vlog +incdir+../config/buildroot ../testbench/testbench-busybear.sv ../src/*/*.sv -suppress 2583
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# start and run simulation
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# remove +acc flag for faster sim during regressions if there is no need to access internal signals
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vopt +acc work.testbench_busybear -o workopt
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vsim workopt -suppress 8852,12070
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view wave
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-- display input and output signals as hexidecimal values
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# Diplays All Signals recursively
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add wave /testbench_busybear/clk
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add wave /testbench_busybear/reset
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add wave -divider
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add wave -hex /testbench_busybear/PCtext
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add wave -hex /testbench_busybear/pcExpected
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add wave -hex /testbench_busybear/dut/hart/ifu/PCD
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add wave -hex /testbench_busybear/dut/hart/ifu/InstrD
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add wave -hex /testbench_busybear/dut/hart/ifu/StallD
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add wave -hex /testbench_busybear/dut/hart/ifu/FlushD
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add wave -hex /testbench_busybear/dut/hart/ifu/StallE
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add wave -hex /testbench_busybear/dut/hart/ifu/FlushE
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add wave -hex /testbench_busybear/dut/hart/ifu/InstrRawD
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add wave /testbench_busybear/CheckInstrD
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add wave /testbench_busybear/lastCheckInstrD
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add wave /testbench_busybear/speculative
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add wave /testbench_busybear/lastPC2
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add wave -divider
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add wave -divider
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add wave /testbench_busybear/dut/uncore/HSELBootTim
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add wave /testbench_busybear/dut/uncore/HSELTim
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add wave /testbench_busybear/dut/uncore/HREADTim
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add wave /testbench_busybear/dut/uncore/dtim/HREADTim0
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add wave /testbench_busybear/dut/uncore/HREADYTim
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add wave -divider
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add wave /testbench_busybear/dut/uncore/HREADBootTim
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add wave /testbench_busybear/dut/uncore/bootdtim/HREADTim0
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add wave /testbench_busybear/dut/uncore/HREADYBootTim
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add wave /testbench_busybear/dut/uncore/HADDR
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add wave /testbench_busybear/dut/uncore/HRESP
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add wave /testbench_busybear/dut/uncore/HREADY
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add wave /testbench_busybear/dut/uncore/HRDATA
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#add wave -hex /testbench_busybear/dut/hart/priv/csr/MTVEC_REG
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#add wave -hex /testbench_busybear/dut/hart/priv/csr/MSTATUS_REG
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#add wave -hex /testbench_busybear/dut/hart/priv/csr/SCOUNTEREN_REG
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#add wave -hex /testbench_busybear/dut/hart/priv/csr/MIE_REG
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#add wave -hex /testbench_busybear/dut/hart/priv/csr/MIDELEG_REG
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#add wave -hex /testbench_busybear/dut/hart/priv/csr/MEDELEG_REG
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add wave -divider
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# registers!
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add wave -hex /testbench_busybear/regExpected
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add wave -hex /testbench_busybear/regNumExpected
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add wave -hex /testbench_busybear/HWRITE
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add wave -hex /testbench_busybear/dut/hart/MemRWM[1]
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add wave -hex /testbench_busybear/HWDATA
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add wave -hex /testbench_busybear/HRDATA
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add wave -hex /testbench_busybear/HADDR
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add wave -hex /testbench_busybear/readAdrExpected
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add wave -hex /testbench_busybear/dut/hart/ieu/dp/regf/rf[1]
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add wave -hex /testbench_busybear/dut/hart/ieu/dp/regf/rf[2]
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add wave -hex /testbench_busybear/dut/hart/ieu/dp/regf/rf[3]
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add wave -hex /testbench_busybear/dut/hart/ieu/dp/regf/rf[4]
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add wave -hex /testbench_busybear/dut/hart/ieu/dp/regf/rf[5]
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add wave -hex /testbench_busybear/dut/hart/ieu/dp/regf/rf[6]
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add wave -hex /testbench_busybear/dut/hart/ieu/dp/regf/rf[7]
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add wave -hex /testbench_busybear/dut/hart/ieu/dp/regf/rf[8]
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add wave -hex /testbench_busybear/dut/hart/ieu/dp/regf/rf[9]
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add wave -hex /testbench_busybear/dut/hart/ieu/dp/regf/rf[10]
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add wave -hex /testbench_busybear/dut/hart/ieu/dp/regf/rf[11]
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add wave -hex /testbench_busybear/dut/hart/ieu/dp/regf/rf[12]
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add wave -hex /testbench_busybear/dut/hart/ieu/dp/regf/rf[13]
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add wave -hex /testbench_busybear/dut/hart/ieu/dp/regf/rf[14]
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add wave -hex /testbench_busybear/dut/hart/ieu/dp/regf/rf[15]
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add wave -hex /testbench_busybear/dut/hart/ieu/dp/regf/rf[16]
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add wave -hex /testbench_busybear/dut/hart/ieu/dp/regf/rf[17]
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add wave -hex /testbench_busybear/dut/hart/ieu/dp/regf/rf[18]
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add wave -hex /testbench_busybear/dut/hart/ieu/dp/regf/rf[19]
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add wave -hex /testbench_busybear/dut/hart/ieu/dp/regf/rf[20]
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add wave -hex /testbench_busybear/dut/hart/ieu/dp/regf/rf[21]
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add wave -hex /testbench_busybear/dut/hart/ieu/dp/regf/rf[22]
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add wave -hex /testbench_busybear/dut/hart/ieu/dp/regf/rf[23]
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add wave -hex /testbench_busybear/dut/hart/ieu/dp/regf/rf[24]
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add wave -hex /testbench_busybear/dut/hart/ieu/dp/regf/rf[25]
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||||
add wave -hex /testbench_busybear/dut/hart/ieu/dp/regf/rf[26]
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||||
add wave -hex /testbench_busybear/dut/hart/ieu/dp/regf/rf[27]
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||||
add wave -hex /testbench_busybear/dut/hart/ieu/dp/regf/rf[28]
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||||
add wave -hex /testbench_busybear/dut/hart/ieu/dp/regf/rf[29]
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||||
add wave -hex /testbench_busybear/dut/hart/ieu/dp/regf/rf[30]
|
||||
add wave -hex /testbench_busybear/dut/hart/ieu/dp/regf/rf[31]
|
||||
add wave /testbench_busybear/InstrFName
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||||
add wave -hex /testbench_busybear/dut/hart/ifu/PCD
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||||
#add wave -hex /testbench_busybear/dut/hart/ifu/InstrD
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||||
add wave /testbench_busybear/InstrDName
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||||
#add wave -divider
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||||
add wave -hex /testbench_busybear/dut/hart/ifu/PCE
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##add wave -hex /testbench_busybear/dut/hart/ifu/InstrE
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||||
add wave /testbench_busybear/InstrEName
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#add wave -hex /testbench_busybear/dut/hart/ieu/dp/SrcAE
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||||
#add wave -hex /testbench_busybear/dut/hart/ieu/dp/SrcBE
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add wave -hex /testbench_busybear/dut/hart/ieu/dp/ALUResultE
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||||
#add wave /testbench_busybear/dut/hart/ieu/dp/PCSrcE
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#add wave -divider
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||||
add wave -hex /testbench_busybear/dut/hart/ifu/PCM
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||||
##add wave -hex /testbench_busybear/dut/hart/ifu/InstrM
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||||
add wave /testbench_busybear/InstrMName
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||||
#add wave /testbench_busybear/dut/hart/dmem/dtim/memwrite
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||||
#add wave -hex /testbench_busybear/dut/hart/dmem/AdrM
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||||
#add wave -hex /testbench_busybear/dut/hart/dmem/WriteDataM
|
||||
#add wave -divider
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||||
add wave -hex /testbench_busybear/PCW
|
||||
##add wave -hex /testbench_busybear/dut/hart/ifu/InstrW
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||||
add wave /testbench_busybear/InstrWName
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||||
#add wave /testbench_busybear/dut/hart/ieu/dp/RegWriteW
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||||
#add wave -hex /testbench_busybear/dut/hart/ieu/dp/ResultW
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||||
#add wave -hex /testbench_busybear/dut/hart/ieu/dp/RdW
|
||||
#add wave -divider
|
||||
##add ww
|
||||
add wave -hex -r /testbench_busybear/*
|
||||
#
|
||||
#-- Set Wave Output Items
|
||||
#TreeUpdate [SetDefaultTree]
|
||||
#WaveRestoreZoom {0 ps} {100 ps}
|
||||
#configure wave -namecolwidth 250
|
||||
#configure wave -valuecolwidth 120
|
||||
#configure wave -justifyvalue left
|
||||
#configure wave -signalnamewidth 0
|
||||
#configure wave -snapdistance 10
|
||||
#configure wave -datasetprefix 0
|
||||
#configure wave -rowmargin 4
|
||||
#configure wave -childrowmargin 2
|
||||
#set DefaultRadix hexadecimal
|
||||
#
|
||||
#-- Run the Simulation
|
||||
run -all
|
||||
##quit
|
||||
@ -39,7 +39,7 @@ module testbench_busybear();
|
||||
// read pc trace file
|
||||
integer data_file_PC, scan_file_PC;
|
||||
initial begin
|
||||
data_file_PC = $fopen("/courses/e190ax/busybear_boot_new/parsedPC.txt", "r");
|
||||
data_file_PC = $fopen({`BUSYBEAR_TEST_VECTORS,"parsedPC.txt"}, "r");
|
||||
if (data_file_PC == 0) begin
|
||||
$display("file couldn't be opened");
|
||||
$stop;
|
||||
@ -48,7 +48,7 @@ module testbench_busybear();
|
||||
|
||||
integer data_file_PCW, scan_file_PCW;
|
||||
initial begin
|
||||
data_file_PCW = $fopen("/courses/e190ax/busybear_boot_new/parsedPC.txt", "r");
|
||||
data_file_PCW = $fopen({`BUSYBEAR_TEST_VECTORS,"parsedPC.txt"}, "r");
|
||||
if (data_file_PCW == 0) begin
|
||||
$display("file couldn't be opened");
|
||||
$stop;
|
||||
@ -58,7 +58,7 @@ module testbench_busybear();
|
||||
// read register trace file
|
||||
integer data_file_rf, scan_file_rf;
|
||||
initial begin
|
||||
data_file_rf = $fopen("/courses/e190ax/busybear_boot_new/parsedRegs.txt", "r");
|
||||
data_file_rf = $fopen({`BUSYBEAR_TEST_VECTORS,"parsedRegs.txt"}, "r");
|
||||
if (data_file_rf == 0) begin
|
||||
$display("file couldn't be opened");
|
||||
$stop;
|
||||
@ -68,7 +68,7 @@ module testbench_busybear();
|
||||
// read CSR trace file
|
||||
integer data_file_csr, scan_file_csr;
|
||||
initial begin
|
||||
data_file_csr = $fopen("/courses/e190ax/busybear_boot_new/parsedCSRs.txt", "r");
|
||||
data_file_csr = $fopen({`BUSYBEAR_TEST_VECTORS,"parsedCSRs.txt"}, "r");
|
||||
if (data_file_csr == 0) begin
|
||||
$display("file couldn't be opened");
|
||||
$stop;
|
||||
@ -78,7 +78,7 @@ module testbench_busybear();
|
||||
// read memreads trace file
|
||||
integer data_file_memR, scan_file_memR;
|
||||
initial begin
|
||||
data_file_memR = $fopen("/courses/e190ax/busybear_boot_new/parsedMemRead.txt", "r");
|
||||
data_file_memR = $fopen({`BUSYBEAR_TEST_VECTORS,"parsedMemRead.txt"}, "r");
|
||||
if (data_file_memR == 0) begin
|
||||
$display("file couldn't be opened");
|
||||
$stop;
|
||||
@ -88,7 +88,7 @@ module testbench_busybear();
|
||||
// read memwrite trace file
|
||||
integer data_file_memW, scan_file_memW;
|
||||
initial begin
|
||||
data_file_memW = $fopen("/courses/e190ax/busybear_boot_new/parsedMemWrite.txt", "r");
|
||||
data_file_memW = $fopen({`BUSYBEAR_TEST_VECTORS,"parsedMemWrite.txt"}, "r");
|
||||
if (data_file_memW == 0) begin
|
||||
$display("file couldn't be opened");
|
||||
$stop;
|
||||
@ -97,8 +97,8 @@ module testbench_busybear();
|
||||
|
||||
// initial loading of memories
|
||||
initial begin
|
||||
$readmemh("/courses/e190ax/busybear_boot_new/bootmem.txt", dut.uncore.bootdtim.RAM, 'h1000 >> 3);
|
||||
$readmemh("/courses/e190ax/busybear_boot_new/ram.txt", dut.uncore.dtim.RAM);
|
||||
$readmemh({`BUSYBEAR_TEST_VECTORS,"bootmem.txt"}, dut.uncore.bootdtim.RAM, 'h1000 >> 3);
|
||||
$readmemh({`BUSYBEAR_TEST_VECTORS,"ram.txt"}, dut.uncore.dtim.RAM);
|
||||
$readmemb(`TWO_BIT_PRELOAD, dut.hart.ifu.bpred.Predictor.DirPredictor.PHT.memory);
|
||||
$readmemb(`BTB_PRELOAD, dut.hart.ifu.bpred.TargetPredictor.memory.memory);
|
||||
end
|
||||
|
||||
Loading…
Reference in New Issue
Block a user