start to add buildroot testbench

This still uses testbench-busybear.sv
I think it might be time to finally rename nearly 'busybear' thing to 'linux'

wally-pipelined/config/buildroot/wally-config.vh

@@ -0,0 +1,107 @@
+//////////////////////////////////////////
+// busybear-config.vh
+//
+// Written: David_Harris@hmc.edu 4 January 2021
+// Modified: 
+//
+// Purpose: Specify which features are configured
+//          Macros to determine which modes are supported based on MISA
+// 
+// A component of the Wally configurable RISC-V project.
+// 
+// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
+//
+// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
+// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, 
+// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software 
+// is furnished to do so, subject to the following conditions:
+//
+// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
+//
+// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 
+// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 
+// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT 
+// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+///////////////////////////////////////////
+
+`define BUSYBEAR
+`define BUSYBEAR_FIX_READ {'h10000005}
+`define BUSYBEAR_TEST_VECTORS "/courses/e190ax/buildroot_boot/"
+// RV32 or RV64: XLEN = 32 or 64
+`define XLEN 64
+
+`define MISA (32'h0014112D)
+`define A_SUPPORTED ((`MISA >> 0) % 2 == 1)
+`define C_SUPPORTED ((`MISA >> 2) % 2 == 1)
+`define D_SUPPORTED ((`MISA >> 3) % 2 == 1)
+`define F_SUPPORTED ((`MISA >> 5) % 2 == 1)
+`define M_SUPPORTED ((`MISA >> 12) % 2 == 1)
+`define S_SUPPORTED ((`MISA >> 18) % 2 == 1)
+`define U_SUPPORTED ((`MISA >> 20) % 2 == 1)
+`define ZCSR_SUPPORTED 1
+`define ZCOUNTERS_SUPPORTED 1
+`define COUNTERS 31
+// N-mode user-level interrupts are depricated per Andrew Waterman 1/13/21
+//`define N_SUPPORTED ((MISA >> 13) % 2 == 1)
+`define N_SUPPORTED 0
+
+`define M_MODE (2'b11)
+`define S_MODE (2'b01)
+`define U_MODE (2'b00)
+
+// Microarchitectural Features
+`define UARCH_PIPELINED 1
+`define UARCH_SUPERSCALR 0
+`define UARCH_SINGLECYCLE 0
+`define MEM_DCACHE 0
+`define MEM_DTIM 1
+`define MEM_ICACHE 0
+`define MEM_VIRTMEM 0
+`define VECTORED_INTERRUPTS_SUPPORTED 1 // Domenico Ottolia 4/15: Support for vectored interrupts in _tvec csrs. Just implemented in src/privileged/trap.sv around line 75. Pretty sure this should be 1.
+
+// Address space
+`define RESET_VECTOR 64'h0000000000001000
+
+// Peripheral Addresses
+// Peripheral memory space extends from BASE to BASE+RANGE
+// Range should be a thermometer code with 0's in the upper bits and 1s in the lower bits
+
+`define BOOTTIMBASE   32'h00000000 //only needs to go from 0x1000 to 0x2FFF, extending to a power of 2
+`define BOOTTIMRANGE  32'h00003FFF
+`define CLINTBASE     32'h02000000
+`define CLINTRANGE    32'h0000FFFF
+`define PLICBASE      32'h0C000000
+`define PLICRANGE     32'h03FFFFFF
+`define UARTBASE      32'h10000000
+`define UARTRANGE     32'h00000007
+`define VBD0BASE      32'h10001000
+`define VBD0RANGE     32'h000001FF
+// differing from Imperas' OVPSim by not having a VND0
+`define GPIOBASE      32'h20000000 
+`define GPIORANGE     32'h000000FF
+`define TIMBASE       32'h80000000
+`define TIMRANGE      32'h07FFFFFF
+// Bus Interface width
+`define AHBW 64
+
+// Test modes
+
+// Tie GPIO outputs back to inputs
+`define GPIO_LOOPBACK_TEST 0
+
+// Busybear special CSR config to match OVPSim
+`define OVPSIM_CSR_CONFIG 1
+
+// Hardware configuration
+`define UART_PRESCALE 1
+
+// Interrupt configuration
+`define PLIC_NUM_SRC 53
+`define PLIC_UART_ID 4
+
+/* verilator lint_off STMTDLY */
+/* verilator lint_off WIDTH */
+
+`define TWO_BIT_PRELOAD "../config/busybear/twoBitPredictor.txt"
+`define BTB_PRELOAD "../config/busybear/BTBPredictor.txt"
+`define BPTYPE "BPGSHARE" // BPGLOBAL or BPTWOBIT or BPGSHARE

wally-pipelined/config/buildroot/wally-constants.vh

@@ -0,0 +1,33 @@
+//////////////////////////////////////////
+// wally-constants.vh
+//
+// Written: tfleming@hmc.edu 4 March 2021
+// Modified:
+//
+// Purpose: Specify certain constants defined in the RISC-V 64-bit architecture.
+//          These macros should not be changed, except in the event of an
+//          update to the architecture or particularly special circumstances.
+//
+// A component of the Wally configurable RISC-V project.
+//
+// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
+//
+// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
+// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy,
+// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software
+// is furnished to do so, subject to the following conditions:
+//
+// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
+//
+// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
+// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
+// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+///////////////////////////////////////////
+
+// Virtual Memory Constants (sv39)
+`define VPN_SEGMENT_BITS 9
+`define VPN_BITS 27
+`define PPN_BITS 44
+`define PPN_HIGH_SEGMENT_BITS 26
+`define PA_BITS  56

wally-pipelined/config/busybear/wally-config.vh

@@ -26,6 +26,7 @@
 
 `define BUSYBEAR
 `define BUSYBEAR_FIX_READ {'h10000005}
+`define BUSYBEAR_TEST_VECTORS "/courses/e190ax/busybear_boot_new/"
 // RV32 or RV64: XLEN = 32 or 64
 `define XLEN 64
 

wally-pipelined/regression/sim-buildroot

@@ -0,0 +1 @@
+vsim -do wally-buildroot.do

wally-pipelined/regression/sim-buildroot-batch

@@ -0,0 +1,3 @@
+vsim -c <<!
+do wally-buildroot-batch.do 
+!

wally-pipelined/regression/wally-buildroot-batch.do

@@ -0,0 +1,39 @@
+# wally-pipelined.do 
+#
+# Modification by Oklahoma State University & Harvey Mudd College
+# Use with testbench_busybear 
+# James Stine, 2008; David Harris 2021
+# Go Cowboys!!!!!!
+#
+# Takes 1:10 to run RV64IC tests using gui
+
+# Use this wally-pipelined.do file to run this example.
+# Either bring up ModelSim and type the following at the "ModelSim>" prompt:
+#     do wally-pipelined.do
+# or, to run from a shell, type the following at the shell prompt:
+#     vsim -do wally-pipelined.do -c
+# (omit the "-c" to see the GUI while running from the shell)
+
+onbreak {resume}
+
+# create library
+if [file exists work-buildroot] {
+    vdel -all -lib work-buildroot
+}
+vlib work-buildroot
+
+# compile source files
+# suppress spurious warnngs about 
+# "Extra checking for conflicts with always_comb done at vopt time"
+# because vsim will run vopt
+vlog +incdir+../config/buildroot ../testbench/testbench-busybear.sv ../src/*/*.sv -suppress 2583
+
+
+# start and run simulation
+# remove +acc flag for faster sim during regressions if there is no need to access internal signals
+vopt work.testbench_busybear -o workopt 
+
+vsim workopt -suppress 8852,12070
+
+run -all
+quit

wally-pipelined/regression/wally-buildroot.do

@@ -0,0 +1,166 @@
+# wally-pipelined.do 
+#
+# Modification by Oklahoma State University & Harvey Mudd College
+# Use with testbench_busybear 
+# James Stine, 2008; David Harris 2021
+# Go Cowboys!!!!!!
+#
+# Takes 1:10 to run RV64IC tests using gui
+
+# Use this wally-pipelined.do file to run this example.
+# Either bring up ModelSim and type the following at the "ModelSim>" prompt:
+#     do wally-pipelined.do
+# or, to run from a shell, type the following at the shell prompt:
+#     vsim -do wally-pipelined.do -c
+# (omit the "-c" to see the GUI while running from the shell)
+
+onbreak {resume}
+
+# create library
+if [file exists work-buildroot] {
+    vdel -all -lib work-buildroot
+}
+vlib work-buildroot
+
+# compile source files
+# suppress spurious warnngs about 
+# "Extra checking for conflicts with always_comb done at vopt time"
+# because vsim will run vopt
+vlog +incdir+../config/buildroot ../testbench/testbench-busybear.sv ../src/*/*.sv -suppress 2583
+
+
+# start and run simulation
+# remove +acc flag for faster sim during regressions if there is no need to access internal signals
+vopt +acc work.testbench_busybear -o workopt 
+
+vsim workopt -suppress 8852,12070
+
+
+view wave
+
+-- display input and output signals as hexidecimal values
+# Diplays All Signals recursively
+add wave /testbench_busybear/clk
+add wave /testbench_busybear/reset
+add wave -divider
+add wave -hex /testbench_busybear/PCtext
+add wave -hex /testbench_busybear/pcExpected
+add wave -hex /testbench_busybear/dut/hart/ifu/PCD
+add wave -hex /testbench_busybear/dut/hart/ifu/InstrD
+add wave -hex /testbench_busybear/dut/hart/ifu/StallD
+add wave -hex /testbench_busybear/dut/hart/ifu/FlushD
+add wave -hex /testbench_busybear/dut/hart/ifu/StallE
+add wave -hex /testbench_busybear/dut/hart/ifu/FlushE
+add wave -hex /testbench_busybear/dut/hart/ifu/InstrRawD
+add wave /testbench_busybear/CheckInstrD
+add wave /testbench_busybear/lastCheckInstrD
+add wave /testbench_busybear/speculative
+add wave /testbench_busybear/lastPC2
+add wave -divider
+add wave -divider
+add wave /testbench_busybear/dut/uncore/HSELBootTim
+add wave /testbench_busybear/dut/uncore/HSELTim
+add wave /testbench_busybear/dut/uncore/HREADTim
+add wave /testbench_busybear/dut/uncore/dtim/HREADTim0
+add wave /testbench_busybear/dut/uncore/HREADYTim
+add wave -divider
+add wave /testbench_busybear/dut/uncore/HREADBootTim
+add wave /testbench_busybear/dut/uncore/bootdtim/HREADTim0
+add wave /testbench_busybear/dut/uncore/HREADYBootTim
+add wave /testbench_busybear/dut/uncore/HADDR
+add wave /testbench_busybear/dut/uncore/HRESP
+add wave /testbench_busybear/dut/uncore/HREADY
+add wave /testbench_busybear/dut/uncore/HRDATA
+#add wave -hex /testbench_busybear/dut/hart/priv/csr/MTVEC_REG
+#add wave -hex /testbench_busybear/dut/hart/priv/csr/MSTATUS_REG
+#add wave -hex /testbench_busybear/dut/hart/priv/csr/SCOUNTEREN_REG
+#add wave -hex /testbench_busybear/dut/hart/priv/csr/MIE_REG
+#add wave -hex /testbench_busybear/dut/hart/priv/csr/MIDELEG_REG
+#add wave -hex /testbench_busybear/dut/hart/priv/csr/MEDELEG_REG
+add wave -divider
+# registers!
+add wave -hex /testbench_busybear/regExpected
+add wave -hex /testbench_busybear/regNumExpected
+add wave -hex /testbench_busybear/HWRITE
+add wave -hex /testbench_busybear/dut/hart/MemRWM[1]
+add wave -hex /testbench_busybear/HWDATA
+add wave -hex /testbench_busybear/HRDATA
+add wave -hex /testbench_busybear/HADDR
+add wave -hex /testbench_busybear/readAdrExpected
+add wave -hex /testbench_busybear/dut/hart/ieu/dp/regf/rf[1]
+add wave -hex /testbench_busybear/dut/hart/ieu/dp/regf/rf[2]
+add wave -hex /testbench_busybear/dut/hart/ieu/dp/regf/rf[3]
+add wave -hex /testbench_busybear/dut/hart/ieu/dp/regf/rf[4]
+add wave -hex /testbench_busybear/dut/hart/ieu/dp/regf/rf[5]
+add wave -hex /testbench_busybear/dut/hart/ieu/dp/regf/rf[6]
+add wave -hex /testbench_busybear/dut/hart/ieu/dp/regf/rf[7]
+add wave -hex /testbench_busybear/dut/hart/ieu/dp/regf/rf[8]
+add wave -hex /testbench_busybear/dut/hart/ieu/dp/regf/rf[9]
+add wave -hex /testbench_busybear/dut/hart/ieu/dp/regf/rf[10]
+add wave -hex /testbench_busybear/dut/hart/ieu/dp/regf/rf[11]
+add wave -hex /testbench_busybear/dut/hart/ieu/dp/regf/rf[12]
+add wave -hex /testbench_busybear/dut/hart/ieu/dp/regf/rf[13]
+add wave -hex /testbench_busybear/dut/hart/ieu/dp/regf/rf[14]
+add wave -hex /testbench_busybear/dut/hart/ieu/dp/regf/rf[15]
+add wave -hex /testbench_busybear/dut/hart/ieu/dp/regf/rf[16]
+add wave -hex /testbench_busybear/dut/hart/ieu/dp/regf/rf[17]
+add wave -hex /testbench_busybear/dut/hart/ieu/dp/regf/rf[18]
+add wave -hex /testbench_busybear/dut/hart/ieu/dp/regf/rf[19]
+add wave -hex /testbench_busybear/dut/hart/ieu/dp/regf/rf[20]
+add wave -hex /testbench_busybear/dut/hart/ieu/dp/regf/rf[21]
+add wave -hex /testbench_busybear/dut/hart/ieu/dp/regf/rf[22]
+add wave -hex /testbench_busybear/dut/hart/ieu/dp/regf/rf[23]
+add wave -hex /testbench_busybear/dut/hart/ieu/dp/regf/rf[24]
+add wave -hex /testbench_busybear/dut/hart/ieu/dp/regf/rf[25]
+add wave -hex /testbench_busybear/dut/hart/ieu/dp/regf/rf[26]
+add wave -hex /testbench_busybear/dut/hart/ieu/dp/regf/rf[27]
+add wave -hex /testbench_busybear/dut/hart/ieu/dp/regf/rf[28]
+add wave -hex /testbench_busybear/dut/hart/ieu/dp/regf/rf[29]
+add wave -hex /testbench_busybear/dut/hart/ieu/dp/regf/rf[30]
+add wave -hex /testbench_busybear/dut/hart/ieu/dp/regf/rf[31]
+add wave /testbench_busybear/InstrFName
+add wave -hex /testbench_busybear/dut/hart/ifu/PCD
+#add wave -hex /testbench_busybear/dut/hart/ifu/InstrD
+add wave /testbench_busybear/InstrDName
+#add wave -divider
+add wave -hex /testbench_busybear/dut/hart/ifu/PCE
+##add wave -hex /testbench_busybear/dut/hart/ifu/InstrE
+add wave /testbench_busybear/InstrEName
+#add wave -hex /testbench_busybear/dut/hart/ieu/dp/SrcAE
+#add wave -hex /testbench_busybear/dut/hart/ieu/dp/SrcBE
+add wave -hex /testbench_busybear/dut/hart/ieu/dp/ALUResultE
+#add wave /testbench_busybear/dut/hart/ieu/dp/PCSrcE
+#add wave -divider
+add wave -hex /testbench_busybear/dut/hart/ifu/PCM
+##add wave -hex /testbench_busybear/dut/hart/ifu/InstrM
+add wave /testbench_busybear/InstrMName
+#add wave /testbench_busybear/dut/hart/dmem/dtim/memwrite
+#add wave -hex /testbench_busybear/dut/hart/dmem/AdrM
+#add wave -hex /testbench_busybear/dut/hart/dmem/WriteDataM
+#add wave -divider
+add wave -hex /testbench_busybear/PCW
+##add wave -hex /testbench_busybear/dut/hart/ifu/InstrW
+add wave /testbench_busybear/InstrWName
+#add wave /testbench_busybear/dut/hart/ieu/dp/RegWriteW
+#add wave -hex /testbench_busybear/dut/hart/ieu/dp/ResultW
+#add wave -hex /testbench_busybear/dut/hart/ieu/dp/RdW
+#add wave -divider
+##add ww
+add wave -hex -r /testbench_busybear/*
+#
+#-- Set Wave Output Items 
+#TreeUpdate [SetDefaultTree]
+#WaveRestoreZoom {0 ps} {100 ps}
+#configure wave -namecolwidth 250
+#configure wave -valuecolwidth 120
+#configure wave -justifyvalue left
+#configure wave -signalnamewidth 0
+#configure wave -snapdistance 10
+#configure wave -datasetprefix 0
+#configure wave -rowmargin 4
+#configure wave -childrowmargin 2
+#set DefaultRadix hexadecimal
+#
+#-- Run the Simulation 
+run -all
+##quit

wally-pipelined/testbench/testbench-busybear.sv

@@ -39,7 +39,7 @@ module testbench_busybear();
   // read pc trace file
   integer data_file_PC, scan_file_PC;
   initial begin
-    data_file_PC = $fopen("/courses/e190ax/busybear_boot_new/parsedPC.txt", "r");
+    data_file_PC = $fopen({`BUSYBEAR_TEST_VECTORS,"parsedPC.txt"}, "r");
     if (data_file_PC == 0) begin
       $display("file couldn't be opened");
       $stop;
@@ -48,7 +48,7 @@ module testbench_busybear();
 
   integer data_file_PCW, scan_file_PCW;
   initial begin
-    data_file_PCW = $fopen("/courses/e190ax/busybear_boot_new/parsedPC.txt", "r");
+    data_file_PCW = $fopen({`BUSYBEAR_TEST_VECTORS,"parsedPC.txt"}, "r");
     if (data_file_PCW == 0) begin
       $display("file couldn't be opened");
       $stop;
@@ -58,7 +58,7 @@ module testbench_busybear();
   // read register trace file
   integer data_file_rf, scan_file_rf;
   initial begin
-    data_file_rf = $fopen("/courses/e190ax/busybear_boot_new/parsedRegs.txt", "r");
+    data_file_rf = $fopen({`BUSYBEAR_TEST_VECTORS,"parsedRegs.txt"}, "r");
     if (data_file_rf == 0) begin
       $display("file couldn't be opened");
       $stop;
@@ -68,7 +68,7 @@ module testbench_busybear();
   // read CSR trace file
   integer data_file_csr, scan_file_csr;
   initial begin
-    data_file_csr = $fopen("/courses/e190ax/busybear_boot_new/parsedCSRs.txt", "r");
+    data_file_csr = $fopen({`BUSYBEAR_TEST_VECTORS,"parsedCSRs.txt"}, "r");
     if (data_file_csr == 0) begin
       $display("file couldn't be opened");
       $stop;
@@ -78,7 +78,7 @@ module testbench_busybear();
   // read memreads trace file
   integer data_file_memR, scan_file_memR;
   initial begin
-    data_file_memR = $fopen("/courses/e190ax/busybear_boot_new/parsedMemRead.txt", "r");
+    data_file_memR = $fopen({`BUSYBEAR_TEST_VECTORS,"parsedMemRead.txt"}, "r");
     if (data_file_memR == 0) begin
       $display("file couldn't be opened");
       $stop;
@@ -88,7 +88,7 @@ module testbench_busybear();
   // read memwrite trace file
   integer data_file_memW, scan_file_memW;
   initial begin
-    data_file_memW = $fopen("/courses/e190ax/busybear_boot_new/parsedMemWrite.txt", "r");
+    data_file_memW = $fopen({`BUSYBEAR_TEST_VECTORS,"parsedMemWrite.txt"}, "r");
     if (data_file_memW == 0) begin
       $display("file couldn't be opened");
       $stop;
@@ -97,8 +97,8 @@ module testbench_busybear();
 
   // initial loading of memories
   initial begin
-    $readmemh("/courses/e190ax/busybear_boot_new/bootmem.txt", dut.uncore.bootdtim.RAM, 'h1000 >> 3);
+    $readmemh({`BUSYBEAR_TEST_VECTORS,"bootmem.txt"}, dut.uncore.bootdtim.RAM, 'h1000 >> 3);
-    $readmemh("/courses/e190ax/busybear_boot_new/ram.txt", dut.uncore.dtim.RAM);
+    $readmemh({`BUSYBEAR_TEST_VECTORS,"ram.txt"}, dut.uncore.dtim.RAM);
     $readmemb(`TWO_BIT_PRELOAD, dut.hart.ifu.bpred.Predictor.DirPredictor.PHT.memory);
     $readmemb(`BTB_PRELOAD, dut.hart.ifu.bpred.TargetPredictor.memory.memory);
   end