forked from Github_Repos/cvw
Merge branch 'openhwgroup:main' into code_quality
This commit is contained in:
Limnanthes Serafini
GitHub
commit
4ec28ef32d
@ -47,3 +47,17 @@ coverage exclude -srcfile lzc.sv
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# StallFCause is hardwired to 0
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# StallFCause is hardwired to 0
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#coverage exclude -togglenode /dut/core/hzu/StallFCause
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#coverage exclude -togglenode /dut/core/hzu/StallFCause
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# Excluding peripherals as sources of instructions for the ifu
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coverage exclude -scope /dut/core/ifu/immu/immu/pmachecker/adrdecs/clintdec
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coverage exclude -scope /dut/core/ifu/immu/immu/pmachecker/adrdecs/gpiodec
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coverage exclude -scope /dut/core/ifu/immu/immu/pmachecker/adrdecs/uartdec
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coverage exclude -scope /dut/core/ifu/immu/immu/pmachecker/adrdecs/plicdec
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coverage exclude -scope /dut/core/ifu/immu/immu/pmachecker/adrdecs/bootromdec
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coverage exclude -scope /dut/core/ifu/immu/immu/pmachecker/adrdecs/uncoreramdec
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#Excluding the bootrom, uncoreran, and clint as sources for the lsu
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coverage exclude -scope /dut/core/lsu/dmmu/dmmu/pmachecker/adrdecs/bootromdec
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#set line [GetLineNum ../src/mmu/adrdec.sv "& SizeValid"]
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#coverage exclude -scope /dut/core/lsu/dmmu/dmmu/pmachecker/adrdecs/clintdec -linerange $line-$line -item e 1 -fecexprrow 5
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@ -93,24 +93,24 @@ module fctrl (
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// FRegWrite_FWriteInt_FResSel_PostProcSel_FOpCtrl_FDivStart_IllegalFPUInstr_FCvtInt
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// FRegWrite_FWriteInt_FResSel_PostProcSel_FOpCtrl_FDivStart_IllegalFPUInstr_FCvtInt
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always_comb
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always_comb
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if (STATUS_FS == 2'b00) // FPU instructions are illegal when FPU is disabled
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if (STATUS_FS == 2'b00) // FPU instructions are illegal when FPU is disabled
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ControlsD = `FCTRLW'b0_0_00_xx_000_0_1_0;
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ControlsD = `FCTRLW'b0_0_00_00_000_0_1_0;
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else if (OpD != 7'b0000111 & OpD != 7'b0100111 & ~SupportedFmt)
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else if (OpD != 7'b0000111 & OpD != 7'b0100111 & ~SupportedFmt)
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ControlsD = `FCTRLW'b0_0_00_xx_000_0_1_0; // for anything other than loads and stores, check for supported format
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ControlsD = `FCTRLW'b0_0_00_00_000_0_1_0; // for anything other than loads and stores, check for supported format
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else begin
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else begin
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ControlsD = `FCTRLW'b0_0_00_xx_000_0_1_0; // default: non-implemented instruction
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ControlsD = `FCTRLW'b0_0_00_00_000_0_1_0; // default: non-implemented instruction
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/* verilator lint_off CASEINCOMPLETE */ // default value above has priority so no other default needed
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/* verilator lint_off CASEINCOMPLETE */ // default value above has priority so no other default needed
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case(OpD)
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case(OpD)
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7'b0000111: case(Funct3D)
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7'b0000111: case(Funct3D)
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3'b010: ControlsD = `FCTRLW'b1_0_10_xx_0xx_0_0_0; // flw
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3'b010: ControlsD = `FCTRLW'b1_0_10_00_0xx_0_0_0; // flw
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3'b011: if (`D_SUPPORTED) ControlsD = `FCTRLW'b1_0_10_xx_0xx_0_0_0; // fld
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3'b011: if (`D_SUPPORTED) ControlsD = `FCTRLW'b1_0_10_00_0xx_0_0_0; // fld
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3'b100: if (`Q_SUPPORTED) ControlsD = `FCTRLW'b1_0_10_xx_0xx_0_0_0; // flq
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3'b100: if (`Q_SUPPORTED) ControlsD = `FCTRLW'b1_0_10_00_0xx_0_0_0; // flq
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3'b001: if (`ZFH_SUPPORTED) ControlsD = `FCTRLW'b1_0_10_xx_0xx_0_0_0; // flh
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3'b001: if (`ZFH_SUPPORTED) ControlsD = `FCTRLW'b1_0_10_00_0xx_0_0_0; // flh
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endcase
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endcase
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7'b0100111: case(Funct3D)
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7'b0100111: case(Funct3D)
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3'b010: ControlsD = `FCTRLW'b0_0_10_xx_0xx_0_0_0; // fsw
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3'b010: ControlsD = `FCTRLW'b0_0_10_00_0xx_0_0_0; // fsw
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3'b011: if (`D_SUPPORTED) ControlsD = `FCTRLW'b0_0_10_xx_0xx_0_0_0; // fsd
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3'b011: if (`D_SUPPORTED) ControlsD = `FCTRLW'b0_0_10_00_0xx_0_0_0; // fsd
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3'b100: if (`Q_SUPPORTED) ControlsD = `FCTRLW'b0_0_10_xx_0xx_0_0_0; // fsq
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3'b100: if (`Q_SUPPORTED) ControlsD = `FCTRLW'b0_0_10_00_0xx_0_0_0; // fsq
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3'b001: if (`ZFH_SUPPORTED) ControlsD = `FCTRLW'b0_0_10_xx_0xx_0_0_0; // fsh
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3'b001: if (`ZFH_SUPPORTED) ControlsD = `FCTRLW'b0_0_10_00_0xx_0_0_0; // fsh
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endcase
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endcase
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7'b1000011: ControlsD = `FCTRLW'b1_0_01_10_000_0_0_0; // fmadd
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7'b1000011: ControlsD = `FCTRLW'b1_0_01_10_000_0_0_0; // fmadd
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7'b1000111: ControlsD = `FCTRLW'b1_0_01_10_001_0_0_0; // fmsub
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7'b1000111: ControlsD = `FCTRLW'b1_0_01_10_001_0_0_0; // fmsub
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@ -123,25 +123,25 @@ module fctrl (
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7'b00011??: ControlsD = `FCTRLW'b1_0_01_01_xx0_1_0_0; // fdiv
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7'b00011??: ControlsD = `FCTRLW'b1_0_01_01_xx0_1_0_0; // fdiv
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7'b01011??: if (Rs2D == 5'b0000) ControlsD = `FCTRLW'b1_0_01_01_xx1_1_0_0; // fsqrt
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7'b01011??: if (Rs2D == 5'b0000) ControlsD = `FCTRLW'b1_0_01_01_xx1_1_0_0; // fsqrt
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7'b00100??: case(Funct3D)
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7'b00100??: case(Funct3D)
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3'b000: ControlsD = `FCTRLW'b1_0_00_xx_000_0_0_0; // fsgnj
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3'b000: ControlsD = `FCTRLW'b1_0_00_00_000_0_0_0; // fsgnj
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3'b001: ControlsD = `FCTRLW'b1_0_00_xx_001_0_0_0; // fsgnjn
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3'b001: ControlsD = `FCTRLW'b1_0_00_00_001_0_0_0; // fsgnjn
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3'b010: ControlsD = `FCTRLW'b1_0_00_xx_010_0_0_0; // fsgnjx
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3'b010: ControlsD = `FCTRLW'b1_0_00_00_010_0_0_0; // fsgnjx
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endcase
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endcase
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7'b00101??: case(Funct3D)
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7'b00101??: case(Funct3D)
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3'b000: ControlsD = `FCTRLW'b1_0_00_xx_110_0_0_0; // fmin
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3'b000: ControlsD = `FCTRLW'b1_0_00_00_110_0_0_0; // fmin
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3'b001: ControlsD = `FCTRLW'b1_0_00_xx_101_0_0_0; // fmax
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3'b001: ControlsD = `FCTRLW'b1_0_00_00_101_0_0_0; // fmax
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endcase
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endcase
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7'b10100??: case(Funct3D)
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7'b10100??: case(Funct3D)
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3'b010: ControlsD = `FCTRLW'b0_1_00_xx_010_0_0_0; // feq
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3'b010: ControlsD = `FCTRLW'b0_1_00_00_010_0_0_0; // feq
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3'b001: ControlsD = `FCTRLW'b0_1_00_xx_001_0_0_0; // flt
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3'b001: ControlsD = `FCTRLW'b0_1_00_00_001_0_0_0; // flt
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3'b000: ControlsD = `FCTRLW'b0_1_00_xx_011_0_0_0; // fle
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3'b000: ControlsD = `FCTRLW'b0_1_00_00_011_0_0_0; // fle
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endcase
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endcase
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7'b11100??: if (Funct3D == 3'b001 & Rs2D == 5'b00000)
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7'b11100??: if (Funct3D == 3'b001 & Rs2D == 5'b00000)
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ControlsD = `FCTRLW'b0_1_10_xx_000_0_0_0; // fclass
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ControlsD = `FCTRLW'b0_1_10_00_000_0_0_0; // fclass
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else if (Funct3D == 3'b000 & Rs2D == 5'b00000)
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else if (Funct3D == 3'b000 & Rs2D == 5'b00000)
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ControlsD = `FCTRLW'b0_1_11_xx_000_0_0_0; // fmv.x.w / fmv.x.d to int register
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ControlsD = `FCTRLW'b0_1_11_00_000_0_0_0; // fmv.x.w / fmv.x.d to int register
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7'b111100?: if (Funct3D == 3'b000 & Rs2D == 5'b00000)
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7'b111100?: if (Funct3D == 3'b000 & Rs2D == 5'b00000)
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ControlsD = `FCTRLW'b1_0_00_xx_011_0_0_0; // fmv.w.x / fmv.d.x to fp reg
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ControlsD = `FCTRLW'b1_0_00_00_011_0_0_0; // fmv.w.x / fmv.d.x to fp reg
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7'b0100000: if (Rs2D[4:2] == 3'b000 & SupportedFmt2 & Rs2D[1:0] != 2'b00)
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7'b0100000: if (Rs2D[4:2] == 3'b000 & SupportedFmt2 & Rs2D[1:0] != 2'b00)
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ControlsD = `FCTRLW'b1_0_01_00_000_0_0_0; // fcvt.s.(d/q/h)
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ControlsD = `FCTRLW'b1_0_01_00_000_0_0_0; // fcvt.s.(d/q/h)
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7'b0100001: if (Rs2D[4:2] == 3'b000 & SupportedFmt2 & Rs2D[1:0] != 2'b01)
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7'b0100001: if (Rs2D[4:2] == 3'b000 & SupportedFmt2 & Rs2D[1:0] != 2'b01)
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@ -242,17 +242,20 @@ module fctrl (
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// X - all except int->fp, store, load, mv int->fp
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// X - all except int->fp, store, load, mv int->fp
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assign XEnD = ~(((FResSelD==2'b10)&~FWriteIntD)| // load/store
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assign XEnD = ~(((FResSelD==2'b10)&~FWriteIntD)| // load/store
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((FResSelD==2'b11)&FRegWriteD)| // mv int to float
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((FResSelD==2'b00)&FRegWriteD&(OpCtrlD==3'b011))| // mv int to float - There was an issue here, this condition was not refering to mv int -> fp // ((FResSelD==2'b11)&FRegWriteD)|
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((FResSelD==2'b01)&(PostProcSelD==2'b00)&OpCtrlD[2])); // cvt int to float
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((FResSelD==2'b01)&(PostProcSelD==2'b00)&OpCtrlD[2])); // cvt int to float
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// Y - all except cvt, mv, load, class, sqrt
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// Y - all except cvt, mv, load, class, sqrt
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assign YEnD = ~(((FResSelD==2'b10)&(FWriteIntD|FRegWriteD))| // load or class
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assign YEnD = ~(((FResSelD==2'b10)&(FWriteIntD|FRegWriteD))| // load or class
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(FResSelD==2'b11)| // mv both ways
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((FResSelD==2'b00)&FRegWriteD&(OpCtrlD==3'b011))| // mv int to float as above // previously mv both ways - Another issue here, previously (FResSelD==2'b11)| does not cover mv both way int-> fp and fp-> int
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((FResSelD==2'b11)&(PostProcSelD==2'b00))| // mv float to int // mv both ways
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((FResSelD==2'b01)&((PostProcSelD==2'b00)|((PostProcSelD==2'b01)&OpCtrlD[0])))); // cvt both or sqrt
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((FResSelD==2'b01)&((PostProcSelD==2'b00)|((PostProcSelD==2'b01)&OpCtrlD[0])))); // cvt both or sqrt
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// Removed (FResSelD==2'b11)| removed to avoid redundancy
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// Z - fma ops only
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// Z - fma ops only
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assign ZEnD = (PostProcSelD==2'b10)&(FResSelD==2'b01)&(~OpCtrlD[2]|OpCtrlD[1]); // fma, add, sub
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assign ZEnD = (PostProcSelD==2'b10)&(~OpCtrlD[2]|OpCtrlD[1]); // fma, add, sub // Removed &(FResSelD==2'b01) because it' redundant, Changed all the xx PostProcSelD to 00 to avoid unnecessary contention errors.
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// Final Res Sel:
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// Final Res Sel:
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// fp int
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// fp int
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@ -52,7 +52,8 @@ string tvpaths[] = '{
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"fpu",
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"fpu",
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"lsu",
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"lsu",
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"vm64check",
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"vm64check",
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"pmp"
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"pmp",
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"tlbKP"
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};
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};
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|
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string coremark[] = '{
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string coremark[] = '{
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@ -30,4 +30,4 @@ main:
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|
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sfence.vma x0, x0 // sfence.vma to assert TLBFlush
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sfence.vma x0, x0 // sfence.vma to assert TLBFlush
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|
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j done
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j done
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143
tests/coverage/tlbKP.S
Normal file
143
tests/coverage/tlbKP.S
Normal file
@ -0,0 +1,143 @@
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///////////////////////////////////////////
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// lsu_test.S
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//
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// Written: mmendozamanriquez@hmc.edu 4 April 2023
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|
// nlimpert@hmc.edu
|
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//
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// Purpose: Test coverage for LSU
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//
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// A component of the CORE-V-WALLY configurable RISC-V project.
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//
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// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
|
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|
//
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|
// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
|
||||||
|
//
|
||||||
|
// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
|
||||||
|
// except in compliance with the License, or, at your option, the Apache License version 2.0. You
|
||||||
|
// may obtain a copy of the License at
|
||||||
|
//
|
||||||
|
// https://solderpad.org/licenses/SHL-2.1/
|
||||||
|
//
|
||||||
|
// Unless required by applicable law or agreed to in writing, any work distributed under the
|
||||||
|
// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
|
||||||
|
// either express or implied. See the License for the specific language governing permissions
|
||||||
|
// and limitations under the License.
|
||||||
|
////////////////////////////////////////////////////////////////////////////////////////////////
|
||||||
|
|
||||||
|
// load code to initalize stack, handle interrupts, terminate
|
||||||
|
|
||||||
|
#include "WALLY-init-lib.h"
|
||||||
|
|
||||||
|
# run-elf.bash find this in project description
|
||||||
|
main:
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||||||
|
# Page table root address at 0x80010000
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|
li t5, 0x9000000000080010
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csrw satp, t5
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|
|
||||||
|
# sfence.vma x0, x0
|
||||||
|
|
||||||
|
# switch to supervisor mode
|
||||||
|
li a0, 1
|
||||||
|
ecall
|
||||||
|
|
||||||
|
li t0, 0x80015000
|
||||||
|
|
||||||
|
li t2, 0 # i = 0
|
||||||
|
li t3, 33 # Max amount of Loops = 32
|
||||||
|
|
||||||
|
loop: bge t2, t3, finished # exit loop if i >= loops
|
||||||
|
lw t1, 0(t0)
|
||||||
|
li t4, 0x1000
|
||||||
|
add t0, t0, t4
|
||||||
|
addi t2, t2, 1
|
||||||
|
j loop
|
||||||
|
|
||||||
|
finished:
|
||||||
|
j done
|
||||||
|
|
||||||
|
.data
|
||||||
|
|
||||||
|
.align 16
|
||||||
|
# Page table situated at 0x80010000
|
||||||
|
pagetable:
|
||||||
|
.8byte 0x200044C1 // old page table was 200040 which just pointed to itself! wrong
|
||||||
|
|
||||||
|
.align 12
|
||||||
|
.8byte 0x0000000000000000
|
||||||
|
.8byte 0x00000000200048C1
|
||||||
|
.8byte 0x00000000200048C1
|
||||||
|
|
||||||
|
|
||||||
|
.align 12
|
||||||
|
.8byte 0x0000000020004CC1
|
||||||
|
//.8byte 0x00000200800CF// ADD IN THE MEGAPAGE should 3 nibbles of zeros be removed?
|
||||||
|
|
||||||
|
.align 12
|
||||||
|
#80000000
|
||||||
|
.8byte 0x200000CF
|
||||||
|
.8byte 0x200004CF
|
||||||
|
.8byte 0x200008CF
|
||||||
|
.8byte 0x20000CCF
|
||||||
|
|
||||||
|
.8byte 0x200010CF
|
||||||
|
.8byte 0x200014CF
|
||||||
|
.8byte 0x200018CF
|
||||||
|
.8byte 0x20001CCF
|
||||||
|
|
||||||
|
.8byte 0x200020CF
|
||||||
|
.8byte 0x200024CF
|
||||||
|
.8byte 0x200028CF
|
||||||
|
.8byte 0x20002CCF
|
||||||
|
|
||||||
|
.8byte 0x200030CF
|
||||||
|
.8byte 0x200034CF
|
||||||
|
.8byte 0x200038CF
|
||||||
|
.8byte 0x20003CCF
|
||||||
|
|
||||||
|
.8byte 0x200040CF
|
||||||
|
.8byte 0x200044CF
|
||||||
|
.8byte 0x200048CF
|
||||||
|
.8byte 0x20004CCF
|
||||||
|
|
||||||
|
.8byte 0x200050CF
|
||||||
|
.8byte 0x200054CF
|
||||||
|
.8byte 0x200058CF
|
||||||
|
.8byte 0x20005CCF
|
||||||
|
|
||||||
|
.8byte 0x200060CF
|
||||||
|
.8byte 0x200064CF
|
||||||
|
.8byte 0x200068CF
|
||||||
|
.8byte 0x20006CCF
|
||||||
|
|
||||||
|
.8byte 0x200070CF
|
||||||
|
.8byte 0x200074CF
|
||||||
|
.8byte 0x200078CF
|
||||||
|
.8byte 0x20007CCF
|
||||||
|
|
||||||
|
.8byte 0x200080CF
|
||||||
|
.8byte 0x200084CF
|
||||||
|
.8byte 0x200088CF
|
||||||
|
.8byte 0x20008CCF
|
||||||
|
|
||||||
|
.8byte 0x200090CF
|
||||||
|
.8byte 0x200094CF
|
||||||
|
.8byte 0x200098CF
|
||||||
|
.8byte 0x20009CCF
|
||||||
|
|
||||||
|
.8byte 0x200100CF
|
||||||
|
.8byte 0x200104CF
|
||||||
|
.8byte 0x200108CF
|
||||||
|
.8byte 0x20010CCF
|
||||||
|
|
||||||
|
.8byte 0x200110CF
|
||||||
|
.8byte 0x200114CF
|
||||||
|
.8byte 0x200118CF
|
||||||
|
.8byte 0x20011CCF
|
||||||
|
|
||||||
|
.8byte 0x200120CF
|
||||||
|
.8byte 0x200124CF
|
||||||
|
.8byte 0x200128CF
|
||||||
|
.8byte 0x20012CCF
|
||||||
|
|
||||||
|
.8byte 0x200130CF
|
||||||
|
.8byte 0x200134CF
|
||||||
Loading…
Reference in New Issue
Block a user