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Fixed error in GPIO signature

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This commit is contained in:
slmnemo 2022-06-23 14:12:28 -07:00
parent 66b148b76e
commit 4c8f5fbd89
2 changed files with 3 additions and 3 deletions
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2
tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-gpio-01.reference_output
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@ -11,7 +11,7 @@ A55A0000 # Test interrupt pending bits: high_ip
00000000 # fall_ip
A4AA0000 # input_val
A5FA0000 # high_ip
5BF50000 # low_ip
5BF5FFFF # low_ip
00A00000 # rise_ip
01500000 # fall_ip
00000000 # MEIP

4
tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-gpio-01.S
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@ -109,7 +109,7 @@ SETUP_PLIC
.4byte output_val, 0x5BAA000F, write32_test # change output pattern to check rise/fall interrupts
.4byte input_val, 0xA4AA0000, read32_test # check new output matches expected output
.4byte high_ip, 0xA5FA00000, read32_test # high interrupt pending *** (is this correct?)
.4byte low_ip, 0x5BF50000, read32_test # low interrupt pending should be opposite high for enabled pins
.4byte low_ip, 0x5BF5FFFF, read32_test # low interrupt pending should be opposite high for enabled pins
.4byte rise_ip, 0x00A00000, read32_test # check for changed bits (rising)
.4byte fall_ip, 0x01500000, read32_test # check for changed bits (falling)
.4byte 0x0, 0x00000000, readmip_test # Check no external interrupt has been generated
@ -129,7 +129,7 @@ SETUP_PLIC
.4byte high_ie, 0x00020000, write32_test # enable high interrupt on bit 17, which is pending
.4byte 0x0, 0x00000800, readmip_test # MEIP should be raised
.4byte low_ie, 0x00000000, write32_test # disable high interrupt on bit 17, which is pending
.4byte high_ie, 0x00000000, write32_test # disable high interrupt on bit 17, which is pending
.4byte 0x0, 0x00000000, readmip_test # MEIP should be released
.4byte 0x0, 0x0, terminate_test # terminate tests