formating ahbinterface.

pipelined/src/ebu/ahbcacheinterface.sv

@@ -72,6 +72,7 @@ module ahbcacheinterface #(parameter BEATSPERLINE, LINELEN, LOGWPL, LLENPOVERAHB
   logic [`PA_BITS-1:0]         LocalHADDR;                             // Address after selecting between cached and uncached operation
   logic [LOGWPL-1:0]           BeatCountDelayed;                       // Beat within the cache line in the second (Data) cache stage
   logic                        CaptureEn;                              // Enable updating the Fetch buffer with valid data from HRDATA
+  logic [`AHBW/8-1:0] 		   BusByteMaskM;                           // Byte enables within a word.  For cache request all 1s
   logic [`AHBW-1:0]            PreHWDATA;                              // AHB Address phase write data
 
   genvar                       index;
@@ -106,7 +107,6 @@ module ahbcacheinterface #(parameter BEATSPERLINE, LINELEN, LOGWPL, LLENPOVERAHB
 
   // *** bummer need a second byte mask for bus as it is AHBW rather than LLEN.
   // probably can merge by muxing PAdrM's LLEN/8-1 index bit based on HTRANS being != 0.
-  logic [`AHBW/8-1:0]  BusByteMaskM;
   swbytemask #(`AHBW) busswbytemask(.Size(HSIZE), .Adr(HADDR[$clog2(`AHBW/8)-1:0]), .ByteMask(BusByteMaskM));
   
   flopen #(`AHBW/8) HWSTRBReg(HCLK, HREADY, BusByteMaskM[`AHBW/8-1:0], HWSTRB);

pipelined/src/ebu/ahbinterface.sv

@@ -31,24 +31,24 @@
 `include "wally-config.vh"
 
 module ahbinterface #(parameter LSU = 0) ( // **** modify to use LSU/ifu parameter to control widths of buses
-  input logic                HCLK, HRESETn,
+  input logic 							HCLK, HRESETn,
   // bus interface
-  input logic                HREADY,
+  input logic 							HREADY,       // AHB peripheral ready
-  input logic [`XLEN-1:0]    HRDATA,
+  output logic [1:0] 					HTRANS,       // AHB transaction type, 00: IDLE, 10 NON_SEQ, 11 SEQ
-  output logic [1:0]         HTRANS,
+  output logic 							HWRITE,       // AHB 0: Read operation 1: Write operation 
-  output logic               HWRITE,
+  input logic [`XLEN-1:0] 				HRDATA,       // AHB read data
-  output logic [`XLEN-1:0]   HWDATA,
+  output logic [`XLEN-1:0] 				HWDATA,       // AHB write data
-  output logic [`XLEN/8-1:0] HWSTRB,
+  output logic [`XLEN/8-1:0] 			HWSTRB,       // AHB byte mask
   
   // lsu/ifu interface
-  input logic                Flush,
+  input logic 							Stall,        // Core pipeline is stalled
-  input logic [1:0]          BusRW,
+  input logic 							Flush,        // Pipeline stage flush. Prevents bus transaction from starting
-  input logic [`XLEN/8-1:0]  ByteMask,
+  input logic [1:0] 					BusRW,        // Memory operation read/write control: 10: read, 01: write
-  input logic [`XLEN-1:0]    WriteData,
+  input logic [`XLEN/8-1:0] 			ByteMask,     // Bytes enables within a word
-  input logic                Stall,
+  input logic [`XLEN-1:0] 				WriteData,    // IEU write data for a store
-  output logic               BusStall,
+  output logic 							BusStall,     // Bus is busy with an in flight memory operation
-  output logic               BusCommitted,
+  output logic 							BusCommitted, // Bus is busy with an in flight memory operation and it is not safe to take an interrupt
-  output logic [(LSU ? `XLEN : 32)-1:0]   FetchBuffer
+  output logic [(LSU ? `XLEN : 32)-1:0] FetchBuffer   // Register to hold HRDATA after arriving from the bus
 );
   
   logic                       CaptureEn;