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fix ReadDataM forcing

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bbracker 2022-04-13 15:32:00 -07:00
parent 20c82b6f1a
commit 489ce4269a
1 changed files with 4 additions and 4 deletions
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8
pipelined/testbench/testbench-linux.sv
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@ -27,7 +27,7 @@
`include "wally-config.vh" `include "wally-config.vh"
`define DEBUG_TRACE 0 `define DEBUG_TRACE 2
// Debug Levels // Debug Levels
// 0: don't check against QEMU // 0: don't check against QEMU
// 1: print disagreements with QEMU, but only halt on PCW disagreements // 1: print disagreements with QEMU, but only halt on PCW disagreements
@ -546,11 +546,11 @@ module testbench;
end \ end \
if(`"STAGE`"=="M") begin \ if(`"STAGE`"=="M") begin \
// override on special conditions \ // override on special conditions \
if ((dut.core.lsu.LSUPAdrM == 'h10000002) | (dut.core.lsu.LSUPAdrM == 'h10000005) | (dut.core.lsu.LSUPAdrM == 'h10000006)) \ if ((dut.core.lsu.LSUPAdrM == 'h10000002) | (dut.core.lsu.LSUPAdrM == 'h10000005) | (dut.core.lsu.LSUPAdrM == 'h10000006)) begin \
//$display("%tns, %d instrs: Overwrite UART's LSR in memory stage.", $time, InstrCountW-1); \ $display("%tns, %d instrs: Overwrite UART's LSR in memory stage.", $time, AttemptedInstructionCount); \
if(!NO_IE_MTIME_CHECKPOINT) \ if(!NO_IE_MTIME_CHECKPOINT) \
force dut.core.ieu.dp.ReadDataM = ExpectedMemReadDataM; \ force dut.core.ieu.dp.ReadDataM = ExpectedMemReadDataM; \
else \ end else \
if(!NO_IE_MTIME_CHECKPOINT) \ if(!NO_IE_MTIME_CHECKPOINT) \
release dut.core.ieu.dp.ReadDataM; \ release dut.core.ieu.dp.ReadDataM; \
if(textM.substr(0,5) == "rdtime") begin \ if(textM.substr(0,5) == "rdtime") begin \