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Added IPs to wally.tcl.

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This commit is contained in:
Jacob Pease 2023-01-13 14:36:23 -06:00
parent bb96925374
commit 47c46bc9b5
2 changed files with 3 additions and 73 deletions
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3
fpga/generator/wally.tcl
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@ -16,6 +16,9 @@ read_ip IP/xlnx_ddr4.srcs/sources_1/ip/xlnx_ddr4/xlnx_ddr4.xci
# Added crossbar - Jacob Pease <2023-01-12 Thu> # Added crossbar - Jacob Pease <2023-01-12 Thu>
read_ip IP/xlnx_axi_crossbar.srcs/sources_1/ip/xlnx_axi_crossbar/xlnx_axi_crossbar.xci read_ip IP/xlnx_axi_crossbar.srcs/sources_1/ip/xlnx_axi_crossbar/xlnx_axi_crossbar.xci
read_ip IP/xlnx_axi_dwidth_conv_32to64.srcs/sources_1/ip/xlnx_axi_dwidth_conv_32to64/xlnx_axi_dwidth_conv_32to64.xci
read_ip IP/xlnx_axi_dwidth_conv_64to32.srcs/sources_1/ip/xlnx_axi_dwidth_conv_64to32/xlnx_axi_dwidth_conv_64to32.xci
read_verilog -sv [glob -type f ../../pipelined/src/*/*.sv ../../pipelined/src/*/*/*.sv] read_verilog -sv [glob -type f ../../pipelined/src/*/*.sv ../../pipelined/src/*/*/*.sv]

73
fpga/src/fpgaTop.v
View File

@ -486,79 +486,6 @@ module fpgaTop
.m_axi_rvalid(m_axi_rvalid), .m_axi_rvalid(m_axi_rvalid),
.m_axi_rlast(m_axi_rlast), .m_axi_rlast(m_axi_rlast),
.m_axi_rready(m_axi_rready)); .m_axi_rready(m_axi_rready));
wire [3:0] s00_axi_awid;
wire [7:0] s00_axi_awlen;
wire [2:0] s00_axi_awsize;
wire [1:0] s00_axi_awburst;
wire [3:0] s00_axi_awcache;
wire [31:0] s00_axi_awaddr;
wire [2:0] s00_axi_awprot;
wire s00_axi_awvalid;
wire s00_axi_awready;
wire s00_axi_awlock;
wire [63:0] s00_axi_wdata;
wire [7:0] s00_axi_wstrb;
wire s00_axi_wlast;
wire s00_axi_wvalid;
wire s00_axi_wready;
wire [3:0] s00_axi_bid;
wire [1:0] s00_axi_bresp;
wire s00_axi_bvalid;
wire s00_axi_bready;
wire [3:0] s00_axi_arid;
wire [7:0] s00_axi_arlen;
wire [2:0] s00_axi_arsize;
wire [1:0] s00_axi_arburst;
wire [2:0] s00_axi_arprot;
wire [3:0] s00_axi_arcache;
wire s00_axi_arvalid;
wire [31:0] s00_axi_araddr;
wire s00_axi_arlock;
wire s00_axi_arready;
wire [3:0] s00_axi_rid;
wire [63:0] s00_axi_rdata;
wire [1:0] s00_axi_rresp;
wire s00_axi_rvalid;
wire s00_axi_rlast;
wire s00_axi_rready;
wire [3:0] s01_axi_awid;
wire [7:0] s01_axi_awlen;
wire [2:0] s01_axi_awsize;
wire [1:0] s01_axi_awburst;
wire [3:0] s01_axi_awcache;
wire [31:0] s01_axi_awaddr;
wire [2:0] s01_axi_awprot;
wire s01_axi_awvalid;
wire s01_axi_awready;
wire s01_axi_awlock;
wire [63:0] s01_axi_wdata;
wire [7:0] s01_axi_wstrb;
wire s01_axi_wlast;
wire s01_axi_wvalid;
wire s01_axi_wready;
wire [3:0] s01_axi_bid;
wire [1:0] s01_axi_bresp;
wire s01_axi_bvalid;
wire s01_axi_bready;
wire [3:0] s01_axi_arid;
wire [7:0] s01_axi_arlen;
wire [2:0] s01_axi_arsize;
wire [1:0] s01_axi_arburst;
wire [2:0] s01_axi_arprot;
wire [3:0] s01_axi_arcache;
wire s01_axi_arvalid;
wire [31:0] s01_axi_araddr;
wire s01_axi_arlock;
wire s01_axi_arready;
wire [3:0] s01_axi_rid;
wire [63:0] s01_axi_rdata;
wire [1:0] s01_axi_rresp;
wire s01_axi_rvalid;
wire s01_axi_rlast;
wire s01_axi_rready;
// AXI Crossbar for arbitrating the SDC and CPU -------------- // AXI Crossbar for arbitrating the SDC and CPU --------------
xlnx_axi_crossbar xlnx_axi_crossbar_0 xlnx_axi_crossbar xlnx_axi_crossbar_0