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Renamed states in busfsm to match AHB phases and book names.

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This commit is contained in:
Ross Thompson 2022-09-02 17:12:36 -05:00
parent 15a2fbdd33
commit 472fb5e888
1 changed files with 21 additions and 21 deletions
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42
pipelined/src/ebu/busfsm.sv
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@ -46,39 +46,39 @@ module busfsm
output logic HWRITE output logic HWRITE
); );
typedef enum logic [2:0] {STATE_READY, typedef enum logic [2:0] {ADR_PHASE,
STATE_CAPTURE, DATA_PHASE,
STATE_DELAY} busstatetype; MEM3} busstatetype;
typedef enum logic [1:0] {AHB_IDLE = 2'b00, AHB_BUSY = 2'b01, AHB_NONSEQ = 2'b10, AHB_SEQ = 2'b11} ahbtranstype; typedef enum logic [1:0] {AHB_IDLE = 2'b00, AHB_BUSY = 2'b01, AHB_NONSEQ = 2'b10, AHB_SEQ = 2'b11} ahbtranstype;
(* mark_debug = "true" *) busstatetype BusCurrState, BusNextState; (* mark_debug = "true" *) busstatetype CurrState, NextState;
always_ff @(posedge HCLK) always_ff @(posedge HCLK)
if (~HRESETn) BusCurrState <= #1 STATE_READY; if (~HRESETn) CurrState <= #1 ADR_PHASE;
else BusCurrState <= #1 BusNextState; else CurrState <= #1 NextState;
always_comb begin always_comb begin
case(BusCurrState) case(CurrState)
STATE_READY: if(HREADY & |RW) BusNextState = STATE_CAPTURE; ADR_PHASE: if(HREADY & |RW) NextState = DATA_PHASE;
else BusNextState = STATE_READY; else NextState = ADR_PHASE;
STATE_CAPTURE: if(HREADY) BusNextState = STATE_DELAY; DATA_PHASE: if(HREADY) NextState = MEM3;
else BusNextState = STATE_CAPTURE; else NextState = DATA_PHASE;
STATE_DELAY: if(CPUBusy) BusNextState = STATE_DELAY; MEM3: if(CPUBusy) NextState = MEM3;
else BusNextState = STATE_READY; else NextState = ADR_PHASE;
default: BusNextState = STATE_READY; default: NextState = ADR_PHASE;
endcase endcase
end end
assign BusStall = (BusCurrState == STATE_READY & |RW) | assign BusStall = (CurrState == ADR_PHASE & |RW) |
// (BusCurrState == STATE_CAPTURE & ~RW[0]); // possible optimization here. fails uart test, but i'm not sure the failure is valid. // (CurrState == DATA_PHASE & ~RW[0]); // possible optimization here. fails uart test, but i'm not sure the failure is valid.
(BusCurrState == STATE_CAPTURE); (CurrState == DATA_PHASE);
assign BusCommitted = BusCurrState != STATE_READY; assign BusCommitted = CurrState != ADR_PHASE;
assign HTRANS = (BusCurrState == STATE_READY & HREADY & |RW) | assign HTRANS = (CurrState == ADR_PHASE & HREADY & |RW) |
(BusCurrState == STATE_CAPTURE & ~HREADY) ? AHB_NONSEQ : AHB_IDLE; (CurrState == DATA_PHASE & ~HREADY) ? AHB_NONSEQ : AHB_IDLE;
assign HWRITE = RW[0]; assign HWRITE = RW[0];
assign CaptureEn = BusCurrState == STATE_CAPTURE; assign CaptureEn = CurrState == DATA_PHASE;
endmodule endmodule