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Renamed HPTW_WRITES_SUPPORTED to SVADU_SUPPORTED

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This commit is contained in:
David Harris 2023-02-26 09:38:32 -08:00
parent e3e5100f8d
commit 4579a9d0c2
13 changed files with 18 additions and 18 deletions
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2
config/buildroot/wally-config.vh
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@ -135,7 +135,7 @@
`define BTB_SIZE 10 `define BTB_SIZE 10
`define HPTW_WRITES_SUPPORTED 1 `define SVADU_SUPPORTED 1
// FPU division architecture // FPU division architecture
`define RADIX 32'h4 `define RADIX 32'h4

2
config/fpga/wally-config.vh
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@ -144,7 +144,7 @@
`define BTB_SIZE 10 `define BTB_SIZE 10
`define HPTW_WRITES_SUPPORTED 1 `define SVADU_SUPPORTED 1
// FPU division architecture // FPU division architecture
`define RADIX 32'h4 `define RADIX 32'h4

2
config/rv32e/wally-config.vh
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@ -138,7 +138,7 @@
`define BPRED_SIZE 10 `define BPRED_SIZE 10
`define BTB_SIZE 10 `define BTB_SIZE 10
`define HPTW_WRITES_SUPPORTED 0 `define SVADU_SUPPORTED 0
// FPU division architecture // FPU division architecture
`define RADIX 32'h4 `define RADIX 32'h4

2
config/rv32gc/wally-config.vh
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@ -137,7 +137,7 @@
`define BPRED_SIZE 10 `define BPRED_SIZE 10
`define BTB_SIZE 10 `define BTB_SIZE 10
`define HPTW_WRITES_SUPPORTED 0 `define SVADU_SUPPORTED 0
// FPU division architecture // FPU division architecture
`define RADIX 32'h4 `define RADIX 32'h4

2
config/rv32i/wally-config.vh
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@ -138,7 +138,7 @@
`define BPRED_SIZE 10 `define BPRED_SIZE 10
`define BTB_SIZE 10 `define BTB_SIZE 10
`define HPTW_WRITES_SUPPORTED 0 `define SVADU_SUPPORTED 0
// FPU division architecture // FPU division architecture
`define RADIX 32'h4 `define RADIX 32'h4

2
config/rv32imc/wally-config.vh
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@ -137,7 +137,7 @@
`define BPRED_SIZE 10 `define BPRED_SIZE 10
`define BTB_SIZE 10 `define BTB_SIZE 10
`define HPTW_WRITES_SUPPORTED 0 `define SVADU_SUPPORTED 0
// FPU division architecture // FPU division architecture
`define RADIX 32'h4 `define RADIX 32'h4

2
config/rv64fpquad/wally-config.vh
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@ -140,7 +140,7 @@
`define BPRED_SIZE 10 `define BPRED_SIZE 10
`define BTB_SIZE 10 `define BTB_SIZE 10
`define HPTW_WRITES_SUPPORTED 0 `define SVADU_SUPPORTED 0
// FPU division architecture // FPU division architecture
`define RADIX 32'h4 `define RADIX 32'h4

2
config/rv64gc/wally-config.vh
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@ -140,7 +140,7 @@
`define BPRED_SIZE 10 `define BPRED_SIZE 10
`define BTB_SIZE 10 `define BTB_SIZE 10
`define HPTW_WRITES_SUPPORTED 0 `define SVADU_SUPPORTED 0
// FPU division architecture // FPU division architecture
`define RADIX 32'h4 `define RADIX 32'h4

2
config/rv64i/wally-config.vh
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@ -140,7 +140,7 @@
`define BPRED_SIZE 10 `define BPRED_SIZE 10
`define BTB_SIZE 10 `define BTB_SIZE 10
`define HPTW_WRITES_SUPPORTED 0 `define SVADU_SUPPORTED 0
// FPU division architecture // FPU division architecture
`define RADIX 32'h4 `define RADIX 32'h4

2
src/ifu/spill.sv
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@ -77,7 +77,7 @@ module spill #(
//////////////////////////////////////////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////////////////////////////////////////
assign SpillF = &PCF[$clog2(SPILLTHRESHOLD)+1:1]; assign SpillF = &PCF[$clog2(SPILLTHRESHOLD)+1:1];
assign TakeSpillF = SpillF & ~IFUCacheBusStallD & ~(ITLBMissF | (`HPTW_WRITES_SUPPORTED & InstrDAPageFaultF)); assign TakeSpillF = SpillF & ~IFUCacheBusStallD & ~(ITLBMissF | (`SVADU_SUPPORTED & InstrDAPageFaultF));
always_ff @(posedge clk) always_ff @(posedge clk)
if (reset | FlushD) CurrState <= #1 STATE_READY; if (reset | FlushD) CurrState <= #1 STATE_READY;

10
src/mmu/hptw.sv
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@ -125,7 +125,7 @@ module hptw (
assign ValidLeafPTE = ValidPTE & LeafPTE; assign ValidLeafPTE = ValidPTE & LeafPTE;
assign ValidNonLeafPTE = ValidPTE & ~LeafPTE; assign ValidNonLeafPTE = ValidPTE & ~LeafPTE;
if(`HPTW_WRITES_SUPPORTED) begin : hptwwrites if(`SVADU_SUPPORTED) begin : hptwwrites
logic ReadAccess, WriteAccess; logic ReadAccess, WriteAccess;
logic InvalidRead, InvalidWrite; logic InvalidRead, InvalidWrite;
logic UpperBitsUnequalPageFault; logic UpperBitsUnequalPageFault;
@ -262,7 +262,7 @@ module hptw (
else NextWalkerState = LEAF; else NextWalkerState = LEAF;
L0_RD: if (DCacheStallM) NextWalkerState = L0_RD; L0_RD: if (DCacheStallM) NextWalkerState = L0_RD;
else NextWalkerState = LEAF; else NextWalkerState = LEAF;
LEAF: if (`HPTW_WRITES_SUPPORTED & HPTWDAPageFault) NextWalkerState = UPDATE_PTE; LEAF: if (`SVADU_SUPPORTED & HPTWDAPageFault) NextWalkerState = UPDATE_PTE;
else NextWalkerState = IDLE; else NextWalkerState = IDLE;
UPDATE_PTE: if(DCacheStallM) NextWalkerState = UPDATE_PTE; UPDATE_PTE: if(DCacheStallM) NextWalkerState = UPDATE_PTE;
else NextWalkerState = LEAF; else NextWalkerState = LEAF;
@ -273,8 +273,8 @@ module hptw (
assign SelHPTW = WalkerState != IDLE; assign SelHPTW = WalkerState != IDLE;
assign HPTWStall = (WalkerState != IDLE) | (WalkerState == IDLE & TLBMiss); assign HPTWStall = (WalkerState != IDLE) | (WalkerState == IDLE & TLBMiss);
assign ITLBMissOrDAFaultF = ITLBMissF | (`HPTW_WRITES_SUPPORTED & InstrDAPageFaultF); assign ITLBMissOrDAFaultF = ITLBMissF | (`SVADU_SUPPORTED & InstrDAPageFaultF);
assign DTLBMissOrDAFaultM = DTLBMissM | (`HPTW_WRITES_SUPPORTED & DataDAPageFaultM); assign DTLBMissOrDAFaultM = DTLBMissM | (`SVADU_SUPPORTED & DataDAPageFaultM);
// HTPW address/data/control muxing // HTPW address/data/control muxing
@ -291,7 +291,7 @@ module hptw (
mux2 #(7) funct7mux(Funct7M, 7'b0, SelHPTW, LSUFunct7M); mux2 #(7) funct7mux(Funct7M, 7'b0, SelHPTW, LSUFunct7M);
mux2 #(2) atomicmux(AtomicM, 2'b00, SelHPTW, LSUAtomicM); mux2 #(2) atomicmux(AtomicM, 2'b00, SelHPTW, LSUAtomicM);
mux2 #(`XLEN+2) lsupadrmux(IEUAdrExtM, HPTWAdrExt, SelHPTWAdr, IHAdrM); mux2 #(`XLEN+2) lsupadrmux(IEUAdrExtM, HPTWAdrExt, SelHPTWAdr, IHAdrM);
if(`HPTW_WRITES_SUPPORTED) if(`SVADU_SUPPORTED)
mux2 #(`XLEN) lsuwritedatamux(WriteDataM, PTE, SelHPTW, IHWriteDataM); mux2 #(`XLEN) lsuwritedatamux(WriteDataM, PTE, SelHPTW, IHWriteDataM);
else assign IHWriteDataM = WriteDataM; else assign IHWriteDataM = WriteDataM;

4
src/mmu/tlbcontrol.sv
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@ -76,7 +76,7 @@ module tlbcontrol #(parameter ITLB = 0) (
// only execute non-user mode pages. // only execute non-user mode pages.
assign ImproperPrivilege = ((EffectivePrivilegeMode == `U_MODE) & ~PTE_U) | assign ImproperPrivilege = ((EffectivePrivilegeMode == `U_MODE) & ~PTE_U) |
((EffectivePrivilegeMode == `S_MODE) & PTE_U); ((EffectivePrivilegeMode == `S_MODE) & PTE_U);
if(`HPTW_WRITES_SUPPORTED) begin : hptwwrites if(`SVADU_SUPPORTED) begin : hptwwrites
assign DAPageFault = Translate & TLBHit & ~PTE_A & ~TLBPageFault; assign DAPageFault = Translate & TLBHit & ~PTE_A & ~TLBPageFault;
assign TLBPageFault = (Translate & TLBHit & (ImproperPrivilege | ~PTE_X | UpperBitsUnequalPageFault | Misaligned | ~PTE_V)); assign TLBPageFault = (Translate & TLBHit & (ImproperPrivilege | ~PTE_X | UpperBitsUnequalPageFault | Misaligned | ~PTE_V));
end else begin end else begin
@ -98,7 +98,7 @@ module tlbcontrol #(parameter ITLB = 0) (
// Check for write error. Writes are invalid when the page's write bit is // Check for write error. Writes are invalid when the page's write bit is
// low. // low.
assign InvalidWrite = WriteAccess & ~PTE_W; assign InvalidWrite = WriteAccess & ~PTE_W;
if(`HPTW_WRITES_SUPPORTED) begin : hptwwrites if(`SVADU_SUPPORTED) begin : hptwwrites
assign DAPageFault = Translate & TLBHit & (~PTE_A | WriteAccess & ~PTE_D) & ~TLBPageFault; assign DAPageFault = Translate & TLBHit & (~PTE_A | WriteAccess & ~PTE_D) & ~TLBPageFault;
assign TLBPageFault = (Translate & TLBHit & (ImproperPrivilege | InvalidRead | InvalidWrite | UpperBitsUnequalPageFault | Misaligned | ~PTE_V)); assign TLBPageFault = (Translate & TLBHit & (ImproperPrivilege | InvalidRead | InvalidWrite | UpperBitsUnequalPageFault | Misaligned | ~PTE_V));
end else begin end else begin

2
src/wally/cvw.sv
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@ -101,7 +101,7 @@ package cvw;
parameter BPRED_SUPPORTED = `BPRED_SUPPORTED; parameter BPRED_SUPPORTED = `BPRED_SUPPORTED;
parameter BPRED_TYPE = `BPRED_TYPE; parameter BPRED_TYPE = `BPRED_TYPE;
parameter BPRED_SIZE = `BPRED_SIZE; parameter BPRED_SIZE = `BPRED_SIZE;
parameter HPTW_WRITES_SUPPORTED = `HPTW_WRITES_SUPPORTED; parameter SVADU_SUPPORTED = `SVADU_SUPPORTED;
// parameter = `; // parameter = `;