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Updated fpga constraints.

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This commit is contained in:
Ross Thompson 2023-01-20 20:16:33 -06:00
parent a4822c9f54
commit 442de3f5b7
4 changed files with 7 additions and 7 deletions
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2
fpga/constraints/debug2.xdc
View File

@ -87,7 +87,7 @@ connect_debug_port u_ila_0/probe15 [get_nets [list {wallypipelinedsoc/core/priv.
create_debug_port u_ila_0 probe create_debug_port u_ila_0 probe
set_property port_width 64 [get_debug_ports u_ila_0/probe16] set_property port_width 64 [get_debug_ports u_ila_0/probe16]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe16] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe16]
connect_debug_port u_ila_0/probe16 [get_nets [list {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SCAUSE_REGW[0]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SCAUSE_REGW[1]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SCAUSE_REGW[2]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SCAUSE_REGW[3]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SCAUSE_REGW[4]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SCAUSE_REGW[5]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SCAUSE_REGW[6]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SCAUSE_REGW[7]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SCAUSE_REGW[8]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SCAUSE_REGW[9]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SCAUSE_REGW[10]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SCAUSE_REGW[11]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SCAUSE_REGW[12]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SCAUSE_REGW[13]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SCAUSE_REGW[14]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SCAUSE_REGW[15]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SCAUSE_REGW[16]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SCAUSE_REGW[17]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SCAUSE_REGW[18]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SCAUSE_REGW[19]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SCAUSE_REGW[20]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SCAUSE_REGW[21]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SCAUSE_REGW[22]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SCAUSE_REGW[23]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SCAUSE_REGW[24]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SCAUSE_REGW[25]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SCAUSE_REGW[26]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SCAUSE_REGW[27]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SCAUSE_REGW[28]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SCAUSE_REGW[29]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SCAUSE_REGW[30]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SCAUSE_REGW[31]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SCAUSE_REGW[32]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SCAUSE_REGW[33]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SCAUSE_REGW[34]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SCAUSE_REGW[35]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SCAUSE_REGW[36]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SCAUSE_REGW[37]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SCAUSE_REGW[38]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SCAUSE_REGW[39]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SCAUSE_REGW[40]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SCAUSE_REGW[41]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SCAUSE_REGW[42]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SCAUSE_REGW[43]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SCAUSE_REGW[44]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SCAUSE_REGW[45]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SCAUSE_REGW[46]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SCAUSE_REGW[47]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SCAUSE_REGW[48]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SCAUSE_REGW[49]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SCAUSE_REGW[50]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SCAUSE_REGW[51]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SCAUSE_REGW[52]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SCAUSE_REGW[53]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SCAUSE_REGW[54]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SCAUSE_REGW[55]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SCAUSE_REGW[56]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SCAUSE_REGW[57]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SCAUSE_REGW[58]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SCAUSE_REGW[59]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SCAUSE_REGW[60]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SCAUSE_REGW[61]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SCAUSE_REGW[62]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SCAUSE_REGW[63]} ]] connect_debug_port u_ila_0/probe16 [get_nets [list {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[0]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[1]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[2]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[3]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[4]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[5]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[6]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[7]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[8]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[9]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[10]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[11]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[12]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[13]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[14]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[15]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[16]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[17]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[18]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[19]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[20]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[21]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[22]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[23]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[24]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[25]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[26]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[27]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[28]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[29]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[30]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[31]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[32]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[33]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[34]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[35]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[36]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[37]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[38]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[39]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[40]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[41]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[42]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[43]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[44]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[45]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[46]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[47]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[48]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[49]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[50]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[51]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[52]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[53]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[54]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[55]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[56]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[57]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[58]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[59]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[60]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[61]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[62]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[63]} ]]
create_debug_port u_ila_0 probe create_debug_port u_ila_0 probe

1
fpga/generator/Makefile
View File

@ -26,6 +26,7 @@ SDC:
tar xzf ../src/sdc.tar.gz -C ../src tar xzf ../src/sdc.tar.gz -C ../src
PreProcessFiles: PreProcessFiles:
rm -rf ../src/CopiedFiles_do_not_add_to_repo/
cp -r ../../pipelined/src/ ../src/CopiedFiles_do_not_add_to_repo/ cp -r ../../pipelined/src/ ../src/CopiedFiles_do_not_add_to_repo/
./insert_debug_comment.sh ./insert_debug_comment.sh

9
fpga/generator/insert_debug_comment.sh
View File

@ -26,14 +26,13 @@
# This script copies wally's pipelined#src to fpga#src#CopiedFiles_do_not_add_to_repo # This script copies wally's pipelined#src to fpga#src#CopiedFiles_do_not_add_to_repo
# Then it processes them to add mark_debug on signals needed by the FPGA's ILA. # Then it processes them to add mark_debug on signals needed by the FPGA's ILA.
copiedDir="..#src#CopiedFiles_do_not_add_to_repo" copiedDir="../src/CopiedFiles_do_not_add_to_repo"
while read line; do while read line; do
readarray -d ":" -t StrArray <<< "$line" readarray -d ":" -t StrArray <<< "$line"
file="${copiedDir}#${StrArray[0]}" file="${copiedDir}/${StrArray[0]}"
#signal=`echo "${StrArray[1]}" | awk '{$1=$1};1'`
signal=`echo "${StrArray[1]}" | awk '{$1=$1};1'` signal=`echo "${StrArray[1]}" | awk '{$1=$1};1'`
readarray -d " " -t SigArray <<< $signal readarray -d " " -t SigArray <<< $signal
sigType=`echo "${SigArray[0]}" | awk '{$1=$1};1'` sigType=`echo "${SigArray[0]}" | awk '{$1=$1};1'`
sigName=`echo "${SigArray[1]}" | awk '{$1=$1};1'` sigName=`echo "${SigArray[1]}" | awk '{$1=$1};1'`
find $copiedDir -wholename $file | xargs sed -i "s#\(.*${sigType}.*${sigName}\)#(\* mark_debug = \"true\" \*)\1#g" find $copiedDir -wholename $file | xargs sed -i "s/\(.*${sigType}.*${sigName}\)/(\* mark_debug = \"true\" \*)\1/g"
done < ..#constraints#marked_debug.txt done < ../constraints/marked_debug.txt

2
fpga/generator/wally.tcl
View File

@ -15,7 +15,7 @@ read_ip IP/xlnx_axi_clock_converter.srcs/sources_1/ip/xlnx_axi_clock_converter/x
read_ip IP/xlnx_ddr4.srcs/sources_1/ip/xlnx_ddr4/xlnx_ddr4.xci read_ip IP/xlnx_ddr4.srcs/sources_1/ip/xlnx_ddr4/xlnx_ddr4.xci
read_verilog -sv [glob -type f ../../pipelined/src/*/*.sv ../../pipelined/src/*/*/*.sv] read_verilog -sv [glob -type f ../src/CopiedFiles_do_not_add_to_repo/*/*.sv ../src/CopiedFiles_do_not_add_to_repo/*/*/*.sv]
read_verilog {../src/fpgaTop.v} read_verilog {../src/fpgaTop.v}
read_verilog -sv [glob -type f ../src/sdc/*.sv] read_verilog -sv [glob -type f ../src/sdc/*.sv]