forked from Github_Repos/cvw
Have program which checks for sdc init and issues read, but read done is
not correctly being read back by the software. The error is in how the sdc indicates busy.
This commit is contained in:
Ross Thompson
parent
17c62b7d5a
commit
44196af61a
112
testsBP/fpga-test-dram/Makefile
Normal file
112
testsBP/fpga-test-dram/Makefile
Normal file
@ -0,0 +1,112 @@
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CEXT := c
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CPPEXT := cpp
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AEXT := s
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SEXT := S
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SRCEXT := \([$(CEXT)$(AEXT)$(SEXT)]\|$(CPPEXT)\)
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OBJEXT := o
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DEPEXT := d
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SRCDIR := .
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BUILDDIR := OBJ
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SOURCES ?= $(shell find $(SRCDIR) -type f -regex ".*\.$(SRCEXT)" | sort)
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OBJECTS := $(SOURCES:.$(CEXT)=.$(OBJEXT))
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OBJECTS := $(OBJECTS:.$(AEXT)=.$(OBJEXT))
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OBJECTS := $(OBJECTS:.$(SEXT)=.$(OBJEXT))
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OBJECTS := $(OBJECTS:.$(CPPEXT)=.$(OBJEXT))
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OBJECTS := $(patsubst $(SRCDIR)/%,$(BUILDDIR)/%,$(OBJECTS))
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TARGETDIR := bin
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TARGET := $(TARGETDIR)/blink-led
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ROOT := ..
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LIBRARY_DIRS :=
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LIBRARY_FILES :=
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MARCH :=-march=rv64imfdc
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MABI :=-mabi=lp64d
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LINK_FLAGS :=$(MARCH) $(MABI) -nostartfiles
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LINKER :=$(ROOT)/linker1000.x
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AFLAGS =$(MARCH) $(MABI) -W
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CFLAGS =$(MARCH) $(MABI) -mcmodel=medany -O2
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AS=riscv64-unknown-elf-as
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CC=riscv64-unknown-elf-gcc
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AR=riscv64-unknown-elf-ar
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#Default Make
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all: directories $(TARGET).memfile
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#Remake
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remake: clean all
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#Make the Directories
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directories:
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@mkdir -p $(TARGETDIR)
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@mkdir -p $(BUILDDIR)
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clean:
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rm -rf $(BUILDDIR) $(TARGETDIR) *.memfile *.objdump
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#Needed for building additional library projects
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ifdef LIBRARY_DIRS
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LIBS+=${LIBRARY_DIRS:%=-L%} ${LIBRARY_FILES:%=-l%}
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INC+=${LIBRARY_DIRS:%=-I%}
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${LIBRARY_DIRS}:
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make -C $@ -j 1
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.PHONY: $(LIBRARY_DIRS) $(TARGET)
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endif
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#Pull in dependency info for *existing* .o files
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-include $(OBJECTS:.$(OBJEXT)=.$(DEPEXT))
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#Link
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$(TARGET): $(OBJECTS) $(LIBRARY_DIRS)
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$(CC) $(LINK_FLAGS) -g -o $(TARGET) $(OBJECTS) ${LIBS} -T ${LINKER}
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#Compile
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$(BUILDDIR)/%.$(OBJEXT): $(SRCDIR)/%.$(CEXT)
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@mkdir -p $(dir $@)
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$(CC) $(CFLAGS) $(INC) -c -o $@ $< > $(BUILDDIR)/$*.list
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@$(CC) $(CFLAGS) $(INC) -MM $(SRCDIR)/$*.$(CEXT) > $(BUILDDIR)/$*.$(DEPEXT)
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@cp -f $(BUILDDIR)/$*.$(DEPEXT) $(BUILDDIR)/$*.$(DEPEXT).tmp
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@sed -e 's|.*:|$(BUILDDIR)/$*.$(OBJEXT):|' < $(BUILDDIR)/$*.$(DEPEXT).tmp > $(BUILDDIR)/$*.$(DEPEXT)
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@sed -e 's/.*://' -e 's/\\$$//' < $(BUILDDIR)/$*.$(DEPEXT).tmp | fmt -1 | sed -e 's/^ *//' -e 's/$$/:/' >> $(BUILDDIR)/$*.$(DEPEXT)
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@rm -f $(BUILDDIR)/$*.$(DEPEXT).tmp
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# gcc won't output dependencies for assembly files for some reason
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# most asm files don't have dependencies so the echo will work for now.
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$(BUILDDIR)/%.$(OBJEXT): $(SRCDIR)/%.$(AEXT)
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@mkdir -p $(dir $@)
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$(CC) $(CFLAGS) -c -o $@ $< > $(BUILDDIR)/$*.list
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@echo $@: $< > $(BUILDDIR)/$*.$(DEPEXT)
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$(BUILDDIR)/%.$(OBJEXT): $(SRCDIR)/%.$(SEXT)
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@mkdir -p $(dir $@)
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$(CC) $(CFLAGS) $(INC) -c -o $@ $< > $(BUILDDIR)/$*.list
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@echo $@: $< > $(BUILDDIR)/$*.$(DEPEXT)
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# C++
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$(BUILDDIR)/%.$(OBJEXT): $(SRCDIR)/%.$(CPPEXT)
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@mkdir -p $(dir $@)
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$(CC) $(CFLAGS) $(INC) -c -o $@ $< > $(BUILDDIR)/$*.list
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@$(CC) $(CFLAGS) $(INC) -MM $(SRCDIR)/$*.$(CPPEXT) > $(BUILDDIR)/$*.$(DEPEXT)
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@cp -f $(BUILDDIR)/$*.$(DEPEXT) $(BUILDDIR)/$*.$(DEPEXT).tmp
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@sed -e 's|.*:|$(BUILDDIR)/$*.$(OBJEXT):|' < $(BUILDDIR)/$*.$(DEPEXT).tmp > $(BUILDDIR)/$*.$(DEPEXT)
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@sed -e 's/.*://' -e 's/\\$$//' < $(BUILDDIR)/$*.$(DEPEXT).tmp | fmt -1 | sed -e 's/^ *//' -e 's/$$/:/' >> $(BUILDDIR)/$*.$(DEPEXT)
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@rm -f $(BUILDDIR)/$*.$(DEPEXT).tmp
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# convert to hex
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$(TARGET).memfile: $(TARGET)
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@echo 'Making object dump file.'
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@riscv64-unknown-elf-objdump -D $< > $<.objdump
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@echo 'Making memory file'
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exe2memfile0.pl $<
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extractFunctionRadix.sh $<.objdump
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mkdir -p ../../imperas-riscv-tests/work/rv64BP/
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cp -f $(TARGETDIR)/* ../../imperas-riscv-tests/work/rv64BP/
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130
testsBP/fpga-test-dram/blink-led.s
Normal file
130
testsBP/fpga-test-dram/blink-led.s
Normal file
@ -0,0 +1,130 @@
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PERIOD = 22000000
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#PERIOD = 100
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.section .init
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.global _start
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.type _start, @function
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_start:
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# Initialize global pointer
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.option push
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.option norelax
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1:auipc gp, %pcrel_hi(__global_pointer$)
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addi gp, gp, %pcrel_lo(1b)
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.option pop
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li x1, 0
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li x2, 0
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li x4, 0
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li x5, 0
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li x6, 0
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li x7, 0
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li x8, 0
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li x9, 0
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li x10, 0
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li x11, 0
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li x12, 0
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li x13, 0
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li x14, 0
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li x15, 0
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li x16, 0
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li x17, 0
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li x18, 0
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li x19, 0
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li x20, 0
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li x21, 0
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li x22, 0
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li x23, 0
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li x24, 0
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li x25, 0
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li x26, 0
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li x27, 0
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li x28, 0
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li x29, 0
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li x30, 0
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li x31, 0
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# write to gpio
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li x2, 0xFF
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la x3, 0x10012000
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# +8 is output enable
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# +C is output value
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addi x4, x3, 8
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addi x5, x3, 0xC
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# write initial value of 0xFF to GPO
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sw x2, 0x0(x5)
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# enable output
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sw x2, 0x0(x4)
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# before jumping to led loop
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# lets try writting to dram.
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li x21, 0
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li x23, 4096*16 # 64KB of data
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li x22, 0x80000000
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li x24, 0
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write_loop:
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add x25, x22, x24
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sw x24, 0(x25)
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addi x24, x24, 4
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blt x24, x23, write_loop
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li x24, 0
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read_loop:
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add x25, x22, x24
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lw x21, 0(x25)
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# check value
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bne x21, x24, fail_loop
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addi x24, x24, 4
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#
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blt x24, x23, read_loop
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loop:
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# delay
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li x20, PERIOD
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delay1:
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addi x20, x20, -1
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bge x20, x0, delay1
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# new GPO
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addi x2, x2, 1
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sw x2, 0x0(x5)
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j loop
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fail_loop:
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# delay
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li x20, PERIOD/20
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fail_delay1:
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addi x20, x20, -1
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bge x20, x0, fail_delay1
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# clear GPO
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sw x0, 0x0(x5)
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# delay
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li x20, PERIOD/20
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fail_delay2:
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addi x20, x20, -1
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bge x20, x0, fail_delay2
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# write GPO
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sw x2, 0x0(x5)
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j fail_loop
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112
testsBP/fpga-test-sdc/Makefile
Normal file
112
testsBP/fpga-test-sdc/Makefile
Normal file
@ -0,0 +1,112 @@
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CEXT := c
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CPPEXT := cpp
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AEXT := s
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SEXT := S
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SRCEXT := \([$(CEXT)$(AEXT)$(SEXT)]\|$(CPPEXT)\)
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OBJEXT := o
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DEPEXT := d
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SRCDIR := .
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BUILDDIR := OBJ
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SOURCES ?= $(shell find $(SRCDIR) -type f -regex ".*\.$(SRCEXT)" | sort)
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OBJECTS := $(SOURCES:.$(CEXT)=.$(OBJEXT))
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OBJECTS := $(OBJECTS:.$(AEXT)=.$(OBJEXT))
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OBJECTS := $(OBJECTS:.$(SEXT)=.$(OBJEXT))
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OBJECTS := $(OBJECTS:.$(CPPEXT)=.$(OBJEXT))
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OBJECTS := $(patsubst $(SRCDIR)/%,$(BUILDDIR)/%,$(OBJECTS))
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TARGETDIR := bin
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TARGET := $(TARGETDIR)/fpga-test-sdc
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ROOT := ..
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LIBRARY_DIRS :=
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LIBRARY_FILES :=
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MARCH :=-march=rv64imfdc
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MABI :=-mabi=lp64d
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LINK_FLAGS :=$(MARCH) $(MABI) -nostartfiles
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LINKER :=$(ROOT)/linker1000.x
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AFLAGS =$(MARCH) $(MABI) -W
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CFLAGS =$(MARCH) $(MABI) -mcmodel=medany -O2
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AS=riscv64-unknown-elf-as
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CC=riscv64-unknown-elf-gcc
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AR=riscv64-unknown-elf-ar
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|
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#Default Make
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all: directories $(TARGET).memfile
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||||
|
||||
#Remake
|
||||
remake: clean all
|
||||
|
||||
#Make the Directories
|
||||
directories:
|
||||
@mkdir -p $(TARGETDIR)
|
||||
@mkdir -p $(BUILDDIR)
|
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|
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clean:
|
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rm -rf $(BUILDDIR) $(TARGETDIR) *.memfile *.objdump
|
||||
|
||||
|
||||
#Needed for building additional library projects
|
||||
ifdef LIBRARY_DIRS
|
||||
LIBS+=${LIBRARY_DIRS:%=-L%} ${LIBRARY_FILES:%=-l%}
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INC+=${LIBRARY_DIRS:%=-I%}
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${LIBRARY_DIRS}:
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make -C $@ -j 1
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|
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.PHONY: $(LIBRARY_DIRS) $(TARGET)
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endif
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|
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|
||||
#Pull in dependency info for *existing* .o files
|
||||
-include $(OBJECTS:.$(OBJEXT)=.$(DEPEXT))
|
||||
|
||||
#Link
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$(TARGET): $(OBJECTS) $(LIBRARY_DIRS)
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||||
$(CC) $(LINK_FLAGS) -g -o $(TARGET) $(OBJECTS) ${LIBS} -T ${LINKER}
|
||||
|
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|
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#Compile
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||||
$(BUILDDIR)/%.$(OBJEXT): $(SRCDIR)/%.$(CEXT)
|
||||
@mkdir -p $(dir $@)
|
||||
$(CC) $(CFLAGS) $(INC) -c -o $@ $< > $(BUILDDIR)/$*.list
|
||||
@$(CC) $(CFLAGS) $(INC) -MM $(SRCDIR)/$*.$(CEXT) > $(BUILDDIR)/$*.$(DEPEXT)
|
||||
@cp -f $(BUILDDIR)/$*.$(DEPEXT) $(BUILDDIR)/$*.$(DEPEXT).tmp
|
||||
@sed -e 's|.*:|$(BUILDDIR)/$*.$(OBJEXT):|' < $(BUILDDIR)/$*.$(DEPEXT).tmp > $(BUILDDIR)/$*.$(DEPEXT)
|
||||
@sed -e 's/.*://' -e 's/\\$$//' < $(BUILDDIR)/$*.$(DEPEXT).tmp | fmt -1 | sed -e 's/^ *//' -e 's/$$/:/' >> $(BUILDDIR)/$*.$(DEPEXT)
|
||||
@rm -f $(BUILDDIR)/$*.$(DEPEXT).tmp
|
||||
|
||||
# gcc won't output dependencies for assembly files for some reason
|
||||
# most asm files don't have dependencies so the echo will work for now.
|
||||
$(BUILDDIR)/%.$(OBJEXT): $(SRCDIR)/%.$(AEXT)
|
||||
@mkdir -p $(dir $@)
|
||||
$(CC) $(CFLAGS) -c -o $@ $< > $(BUILDDIR)/$*.list
|
||||
@echo $@: $< > $(BUILDDIR)/$*.$(DEPEXT)
|
||||
|
||||
$(BUILDDIR)/%.$(OBJEXT): $(SRCDIR)/%.$(SEXT)
|
||||
@mkdir -p $(dir $@)
|
||||
$(CC) $(CFLAGS) $(INC) -c -o $@ $< > $(BUILDDIR)/$*.list
|
||||
@echo $@: $< > $(BUILDDIR)/$*.$(DEPEXT)
|
||||
|
||||
# C++
|
||||
$(BUILDDIR)/%.$(OBJEXT): $(SRCDIR)/%.$(CPPEXT)
|
||||
@mkdir -p $(dir $@)
|
||||
$(CC) $(CFLAGS) $(INC) -c -o $@ $< > $(BUILDDIR)/$*.list
|
||||
@$(CC) $(CFLAGS) $(INC) -MM $(SRCDIR)/$*.$(CPPEXT) > $(BUILDDIR)/$*.$(DEPEXT)
|
||||
@cp -f $(BUILDDIR)/$*.$(DEPEXT) $(BUILDDIR)/$*.$(DEPEXT).tmp
|
||||
@sed -e 's|.*:|$(BUILDDIR)/$*.$(OBJEXT):|' < $(BUILDDIR)/$*.$(DEPEXT).tmp > $(BUILDDIR)/$*.$(DEPEXT)
|
||||
@sed -e 's/.*://' -e 's/\\$$//' < $(BUILDDIR)/$*.$(DEPEXT).tmp | fmt -1 | sed -e 's/^ *//' -e 's/$$/:/' >> $(BUILDDIR)/$*.$(DEPEXT)
|
||||
@rm -f $(BUILDDIR)/$*.$(DEPEXT).tmp
|
||||
|
||||
# convert to hex
|
||||
$(TARGET).memfile: $(TARGET)
|
||||
@echo 'Making object dump file.'
|
||||
@riscv64-unknown-elf-objdump -D $< > $<.objdump
|
||||
@echo 'Making memory file'
|
||||
exe2memfile0.pl $<
|
||||
extractFunctionRadix.sh $<.objdump
|
||||
mkdir -p ../../imperas-riscv-tests/work/rv64BP/
|
||||
cp -f $(TARGETDIR)/* ../../imperas-riscv-tests/work/rv64BP/
|
||||
172
testsBP/fpga-test-sdc/test-sdc.s
Normal file
172
testsBP/fpga-test-sdc/test-sdc.s
Normal file
@ -0,0 +1,172 @@
|
||||
PERIOD = 22000000
|
||||
#PERIOD = 100
|
||||
|
||||
.section .init
|
||||
.global _start
|
||||
.type _start, @function
|
||||
|
||||
|
||||
_start:
|
||||
# Initialize global pointer
|
||||
.option push
|
||||
.option norelax
|
||||
1:auipc gp, %pcrel_hi(__global_pointer$)
|
||||
addi gp, gp, %pcrel_lo(1b)
|
||||
.option pop
|
||||
|
||||
li x1, 0
|
||||
li x2, 0
|
||||
li x4, 0
|
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li x5, 0
|
||||
li x6, 0
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li x7, 0
|
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li x8, 0
|
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li x9, 0
|
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li x10, 0
|
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li x11, 0
|
||||
li x12, 0
|
||||
li x13, 0
|
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li x14, 0
|
||||
li x15, 0
|
||||
li x16, 0
|
||||
li x17, 0
|
||||
li x18, 0
|
||||
li x19, 0
|
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li x20, 0
|
||||
li x21, 0
|
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li x22, 0
|
||||
li x23, 0
|
||||
li x24, 0
|
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li x25, 0
|
||||
li x26, 0
|
||||
li x27, 0
|
||||
li x28, 0
|
||||
li x29, 0
|
||||
li x30, 0
|
||||
li x31, 0
|
||||
|
||||
|
||||
# start by writting the clock divider to 4 setting SDC to 25MHz
|
||||
la x3, 0x12100
|
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li x4, -4
|
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sw x4, 0x0(x3)
|
||||
|
||||
# start by writting the clock divider to 1 setting SDC to 100MHZ
|
||||
la x3, 0x12100
|
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li x4, 1
|
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sw x4, 0x0(x3)
|
||||
|
||||
|
||||
# wait until the SDC is done with initialization
|
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li x4, 0x2
|
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wait_sdc_done:
|
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lw x5, 4(x3)
|
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and x5, x5, x4
|
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bne x5, x4, wait_sdc_done
|
||||
|
||||
# now that it is done lets setup for a read
|
||||
li x6, 0x20000000
|
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sd x6, 0x10(x3) # write address register
|
||||
|
||||
# send read by writting to command register
|
||||
li x7, 0x4
|
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sw x7, 0xC(x3)
|
||||
|
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wait_sdc_done_read:
|
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lw x5, 4(x3)
|
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and x5, x5, x4
|
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bne x5, x4, wait_sdc_done_read
|
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|
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# copy data from mailbox
|
||||
copy_sdc:
|
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li x8, 512
|
||||
li x9, 0
|
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ld x10, 0x18(x3) # read the mailbox
|
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addi x9, x9, 1
|
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blt x8, x9, copy_sdc
|
||||
|
||||
|
||||
|
||||
# write to gpio
|
||||
li x2, 0xFF
|
||||
la x3, 0x10012000
|
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|
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# +8 is output enable
|
||||
# +C is output value
|
||||
|
||||
addi x4, x3, 8
|
||||
addi x5, x3, 0xC
|
||||
|
||||
# write initial value of 0xFF to GPO
|
||||
sw x2, 0x0(x5)
|
||||
# enable output
|
||||
sw x2, 0x0(x4)
|
||||
|
||||
# before jumping to led loop
|
||||
# lets try writting to dram.
|
||||
|
||||
li x21, 0
|
||||
li x23, 4096*16 # 64KB of data
|
||||
|
||||
li x22, 0x80000000
|
||||
li x24, 0
|
||||
|
||||
write_loop:
|
||||
add x25, x22, x24
|
||||
sw x24, 0(x25)
|
||||
addi x24, x24, 4
|
||||
blt x24, x23, write_loop
|
||||
|
||||
li x24, 0
|
||||
read_loop:
|
||||
add x25, x22, x24
|
||||
lw x21, 0(x25)
|
||||
|
||||
# check value
|
||||
bne x21, x24, fail_loop
|
||||
|
||||
addi x24, x24, 4
|
||||
|
||||
#
|
||||
blt x24, x23, read_loop
|
||||
|
||||
|
||||
|
||||
loop:
|
||||
|
||||
# delay
|
||||
li x20, PERIOD
|
||||
delay1:
|
||||
addi x20, x20, -1
|
||||
bge x20, x0, delay1
|
||||
|
||||
# new GPO
|
||||
addi x2, x2, 1
|
||||
sw x2, 0x0(x5)
|
||||
|
||||
j loop
|
||||
|
||||
|
||||
fail_loop:
|
||||
|
||||
# delay
|
||||
li x20, PERIOD/20
|
||||
fail_delay1:
|
||||
addi x20, x20, -1
|
||||
bge x20, x0, fail_delay1
|
||||
|
||||
# clear GPO
|
||||
sw x0, 0x0(x5)
|
||||
|
||||
# delay
|
||||
li x20, PERIOD/20
|
||||
fail_delay2:
|
||||
addi x20, x20, -1
|
||||
bge x20, x0, fail_delay2
|
||||
|
||||
# write GPO
|
||||
sw x2, 0x0(x5)
|
||||
|
||||
j fail_loop
|
||||
|
||||
|
||||
193
wally-pipelined/bin/exe2memfile0.pl
Executable file
193
wally-pipelined/bin/exe2memfile0.pl
Executable file
@ -0,0 +1,193 @@
|
||||
#!/usr/bin/perl -w
|
||||
|
||||
# exe2memfile.pl
|
||||
# David_Harris@hmc.edu 26 November 2020
|
||||
# Converts an executable file to a series of 32-bit hex instructions
|
||||
# to read into a Verilog simulation with $readmemh
|
||||
|
||||
use File::stat;
|
||||
use IO::Handle;
|
||||
|
||||
if ($#ARGV == -1) {
|
||||
die("Usage: $0 executable_file");
|
||||
}
|
||||
|
||||
# array to hold contents of memory file
|
||||
my @memfilebytes = (0)*16384*4;
|
||||
my $maxaddress = 0;
|
||||
|
||||
STDOUT->autoflush(1);
|
||||
# *** Ross Thompson I think there is a bug here needs to be +1
|
||||
print ("Processing $#ARGV memfiles: \n");
|
||||
my $frac = $#ARGV/10;
|
||||
for(my $i=0; $i<=$#ARGV; $i++) {
|
||||
if ($i < 10 || $i % $frac == 0) { print ("$i ") };
|
||||
my $fname = $ARGV[$i];
|
||||
# print "fname = $fname";
|
||||
my $ofile = $fname.".objdump";
|
||||
my $memfile = $fname.".memfile";
|
||||
|
||||
my $needsprocessing = 0;
|
||||
if (!-e $memfile) { $needsprocessing = 1; } # create memfile if it doesn't exist
|
||||
else {
|
||||
my $osb = stat($ofile) || die("Can't stat $ofile");
|
||||
my $msb = stat($memfile) || die("Can't stat $memfile");
|
||||
my $otime = $osb->mtime;
|
||||
my $mtime = $msb->mtime;
|
||||
if ($otime > $mtime) { $needsprocessing = 1; } # is memfile out of date?
|
||||
}
|
||||
|
||||
if ($needsprocessing == 1) {
|
||||
open(FILE, $ofile) || die("Can't read $ofile");
|
||||
my $mode = 0; # parse for code
|
||||
my $section = "";
|
||||
my $data = "";
|
||||
my $address;
|
||||
my $first = 0;
|
||||
my $firstAddress;
|
||||
|
||||
# initialize to all zeros;
|
||||
# *** need to fix the zeroing range. Not always 64K
|
||||
for (my $i=0; $i < 65536*4; $i++) {
|
||||
$memfilebytes[$i] = "00";
|
||||
}
|
||||
|
||||
while(<FILE>) {
|
||||
# objdump fill is divided into several .sections of which only some we want to actually process.
|
||||
# In general we want everything except the .comment and .*attributes
|
||||
if (/Disassembly of section (.*):/) {
|
||||
$section = $1;
|
||||
print ("setting section to $section\n");
|
||||
} else {
|
||||
# now check if the section is one we are interested in processing.
|
||||
#if ($section ne ".comment" && $section ne ".riscv.attributes" && $section =~ /\.debug.*/) {
|
||||
if ($section =~ "\.init|\.text|\..*data|\..*bss") {
|
||||
# the structure is: possible space(s) hex number: possible space(s) hex number space(s) junk
|
||||
# there are also lines we need to skip: possible space(s) hex number <string>:
|
||||
if (/^\s*([0-9A-Fa-f]{1,16}):\s+([0-9A-Fa-f]+).*$/) {
|
||||
$address = &fixadr($1);
|
||||
if ($first == 0) {
|
||||
$first = 1;
|
||||
$firstAddress = $address;
|
||||
}
|
||||
$data = $2;
|
||||
&emitData($address, $data);
|
||||
# my $len = length($data);
|
||||
# for (my $i=0; $i<$len/2; $i++) {
|
||||
# $memfilebytes[$address+$i] = substr($data, $len-2-2*$i, 2);
|
||||
# }
|
||||
# print ("Addr $address $data\n");
|
||||
# } elsif (/^\s*\.\.\./) {
|
||||
# print ("Got ...\n");
|
||||
# } else {
|
||||
# print ("No match\n");
|
||||
}
|
||||
}
|
||||
}
|
||||
# # *** this mode stuff does not work if a section is missing or reordered.
|
||||
# if ($mode == 0) { # Parse code
|
||||
# # print("Examining $_\n");
|
||||
# if (/^\s*(\S{1,16}):\s+(\S+)\s+/) {
|
||||
# $address = &fixadr($1);
|
||||
# my $instr = $2;
|
||||
# my $len = length($instr);
|
||||
# for (my $i=0; $i<$len/2; $i++) {
|
||||
# $memfilebytes[$address+$i] = substr($instr, $len-2-2*$i, 2);
|
||||
# }
|
||||
# print ("address $address $instr\n");
|
||||
# }
|
||||
# if (/Disassembly of section .data:/) { $mode = 1;}
|
||||
# } elsif ($mode == 1) { # Parse data segment
|
||||
# if (/^\s*(\S{1,16}):\s+(.*)/) {
|
||||
# $address = &fixadr($1);
|
||||
# # print "addresss $address maxaddress $maxaddress\n";
|
||||
# if ($address > $maxaddress) { $maxaddress = $address; }
|
||||
# my $line = $2;
|
||||
# # merge chunks with spaces
|
||||
# # *** might need to change
|
||||
# $line =~ s/(\S)\s(\S)/$1$2/g;
|
||||
# # strip off comments
|
||||
# $line =~ /^(\S*)/;
|
||||
# $payload = $1;
|
||||
# &emitData($address, $payload);
|
||||
# }
|
||||
# if (/Disassembly of section .comment:/) { $mode = 2; }
|
||||
# } elsif ($mode == 2) { # parse the comment section
|
||||
# if (/Disassembly of section .riscv.attributes:/) { $mode = 3; }
|
||||
# }
|
||||
}
|
||||
close(FILE);
|
||||
$maxaddress = $address + 32; # pad some zeros at the end
|
||||
|
||||
# print to memory file
|
||||
# *** this is a problem
|
||||
if ($fname =~ /rv32/) {
|
||||
open(MEMFILE, ">$memfile") || die("Can't write $memfile");
|
||||
for (my $i=$firstAddress; $i<= $maxaddress; $i = $i + 4) {
|
||||
for ($j=3; $j>=0; $j--) {
|
||||
no warnings 'uninitialized';
|
||||
my $value = $memfilebytes[$i+$j];
|
||||
if ($value eq ""){
|
||||
print MEMFILE "00";
|
||||
} else {
|
||||
print MEMFILE "$memfilebytes[$i+$j]";
|
||||
}
|
||||
}
|
||||
print MEMFILE "\n";
|
||||
}
|
||||
close(MEMFILE);
|
||||
} else {
|
||||
open(MEMFILE, ">$memfile") || die("Can't write $memfile");
|
||||
for (my $i=$firstAddress; $i<= $maxaddress; $i = $i + 8) {
|
||||
for ($j=7; $j>=0; $j--) {
|
||||
no warnings 'uninitialized';
|
||||
my $value = $memfilebytes[$i+$j];
|
||||
if ($value eq ""){
|
||||
print MEMFILE "00";
|
||||
} else {
|
||||
print MEMFILE "$memfilebytes[$i+$j]";
|
||||
}
|
||||
}
|
||||
print MEMFILE "\n";
|
||||
}
|
||||
close(MEMFILE);
|
||||
}
|
||||
}
|
||||
}
|
||||
print("\n");
|
||||
|
||||
sub emitData {
|
||||
# print the data portion of the ELF into a memroy file, including 0s for empty stuff
|
||||
# deal with endianness
|
||||
my $address = shift;
|
||||
my $payload = shift;
|
||||
|
||||
# print("Emitting data. address = $address payload = $payload\n");
|
||||
|
||||
my $len = length($payload);
|
||||
if ($len <= 8) {
|
||||
# print word or halfword
|
||||
for(my $i=0; $i<$len/2; $i++) {
|
||||
my $adr = $address+$i;
|
||||
my $b = substr($payload, $len-2-2*$i, 2);
|
||||
$memfilebytes[$adr] = $b;
|
||||
# print(" $adr $b\n");
|
||||
}
|
||||
} elsif ($len == 12) {
|
||||
# weird case of three halfwords on line
|
||||
&emitData($address, substr($payload, 0, 4));
|
||||
&emitData($address+2, substr($payload, 4, 4));
|
||||
&emitData($address+4, substr($payload, 8, 4));
|
||||
} else {
|
||||
&emitData($address, substr($payload, 0, 8));
|
||||
&emitData($address+4, substr($payload, 8, $len-8));
|
||||
}
|
||||
}
|
||||
|
||||
sub fixadr {
|
||||
# strip off leading 8 from address and convert to decimal
|
||||
# if the leading 8 is not present don't remove.
|
||||
my $adr = shift;
|
||||
#print "addr $adr\n";
|
||||
return hex($adr);
|
||||
}
|
||||
@ -59,15 +59,18 @@
|
||||
// Cache configuration. Sizes should be a power of two
|
||||
// typical configuration 4 ways, 4096 bytes per way, 256 bit or more blocks
|
||||
`define DCACHE_NUMWAYS 4
|
||||
`define DCACHE_WAYSIZEINBYTES 2048
|
||||
`define DCACHE_WAYSIZEINBYTES 4096
|
||||
`define DCACHE_BLOCKLENINBITS 256
|
||||
`define DCACHE_REPLBITS 3
|
||||
`define ICACHE_NUMWAYS 1
|
||||
`define ICACHE_NUMWAYS 4
|
||||
`define ICACHE_WAYSIZEINBYTES 4096
|
||||
`define ICACHE_BLOCKLENINBITS 256
|
||||
|
||||
// Legal number of PMP entries are 0, 16, or 64
|
||||
`define PMP_ENTRIES 64
|
||||
|
||||
// Address space
|
||||
`define RESET_VECTOR 64'h0000000000000000
|
||||
`define RESET_VECTOR 64'h0000000000001000
|
||||
|
||||
// Bus Interface width
|
||||
`define AHBW 64
|
||||
@ -96,7 +99,7 @@
|
||||
`define PLIC_RANGE 56'h03FFFFFF
|
||||
`define SDC_SUPPORTED 1'b1
|
||||
`define SDC_BASE 56'h00012100
|
||||
`define SDC_RANGE 56'h00000020
|
||||
`define SDC_RANGE 56'h0000001F
|
||||
|
||||
// Test modes
|
||||
|
||||
|
||||
49
wally-pipelined/regression/wally-pipelined-fpga.do
Normal file
49
wally-pipelined/regression/wally-pipelined-fpga.do
Normal file
@ -0,0 +1,49 @@
|
||||
# wally-pipelined.do
|
||||
#
|
||||
# Modification by Oklahoma State University & Harvey Mudd College
|
||||
# Use with Testbench
|
||||
# James Stine, 2008; David Harris 2021
|
||||
# Go Cowboys!!!!!!
|
||||
#
|
||||
# Takes 1:10 to run RV64IC tests using gui
|
||||
|
||||
# Use this wally-pipelined.do file to run this example.
|
||||
# Either bring up ModelSim and type the following at the "ModelSim>" prompt:
|
||||
# do wally-pipelined.do
|
||||
# or, to run from a shell, type the following at the shell prompt:
|
||||
# vsim -do wally-pipelined.do -c
|
||||
# (omit the "-c" to see the GUI while running from the shell)
|
||||
|
||||
onbreak {resume}
|
||||
|
||||
# create library
|
||||
if [file exists work] {
|
||||
vdel -all
|
||||
}
|
||||
vlib work
|
||||
|
||||
# compile source files
|
||||
# suppress spurious warnngs about
|
||||
# "Extra checking for conflicts with always_comb done at vopt time"
|
||||
# because vsim will run vopt
|
||||
|
||||
# default to config/rv64ic, but allow this to be overridden at the command line. For example:
|
||||
# do wally-pipelined.do ../config/rv32ic
|
||||
switch $argc {
|
||||
0 {vlog +incdir+../config/rv64BP +incdir+../config/shared ../testbench/testbench-fpga.sv ../testbench/common/*.sv ../src/*/*.sv -suppress 2583}
|
||||
1 {vlog +incdir+$1 +incdir+../config/shared ../testbench/testbench-imperas.sv ../testbench/common/*.sv ../src/*/*.sv -suppress 2583}
|
||||
}
|
||||
# start and run simulation
|
||||
# remove +acc flag for faster sim during regressions if there is no need to access internal signals
|
||||
vopt -fsmdebug +acc -gDEBUG=1 work.testbench -o workopt
|
||||
vsim workopt -fsmdebug
|
||||
|
||||
#profile on
|
||||
|
||||
do wave.do
|
||||
add log -r /*
|
||||
|
||||
-- Run the Simulation
|
||||
#run 1000
|
||||
run -all
|
||||
#quit
|
||||
@ -41,16 +41,16 @@ add wave -noupdate -group HDU -group hazards /testbench/dut/hart/hzu/StoreStallD
|
||||
add wave -noupdate -group HDU -group hazards /testbench/dut/hart/hzu/ICacheStallF
|
||||
add wave -noupdate -group HDU -group hazards /testbench/dut/hart/hzu/LSUStall
|
||||
add wave -noupdate -group HDU -group hazards /testbench/dut/hart/MulDivStallD
|
||||
add wave -noupdate -group HDU -expand -group Flush -color Yellow /testbench/dut/hart/hzu/FlushF
|
||||
add wave -noupdate -group HDU -expand -group Flush -color Yellow /testbench/dut/hart/FlushD
|
||||
add wave -noupdate -group HDU -expand -group Flush -color Yellow /testbench/dut/hart/FlushE
|
||||
add wave -noupdate -group HDU -expand -group Flush -color Yellow /testbench/dut/hart/FlushM
|
||||
add wave -noupdate -group HDU -expand -group Flush -color Yellow /testbench/dut/hart/FlushW
|
||||
add wave -noupdate -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallF
|
||||
add wave -noupdate -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallD
|
||||
add wave -noupdate -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallE
|
||||
add wave -noupdate -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallM
|
||||
add wave -noupdate -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallW
|
||||
add wave -noupdate -group HDU -group Flush -color Yellow /testbench/dut/hart/hzu/FlushF
|
||||
add wave -noupdate -group HDU -group Flush -color Yellow /testbench/dut/hart/FlushD
|
||||
add wave -noupdate -group HDU -group Flush -color Yellow /testbench/dut/hart/FlushE
|
||||
add wave -noupdate -group HDU -group Flush -color Yellow /testbench/dut/hart/FlushM
|
||||
add wave -noupdate -group HDU -group Flush -color Yellow /testbench/dut/hart/FlushW
|
||||
add wave -noupdate -group HDU -group Stall -color Orange /testbench/dut/hart/StallF
|
||||
add wave -noupdate -group HDU -group Stall -color Orange /testbench/dut/hart/StallD
|
||||
add wave -noupdate -group HDU -group Stall -color Orange /testbench/dut/hart/StallE
|
||||
add wave -noupdate -group HDU -group Stall -color Orange /testbench/dut/hart/StallM
|
||||
add wave -noupdate -group HDU -group Stall -color Orange /testbench/dut/hart/StallW
|
||||
add wave -noupdate -group Bpred -color Orange /testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/GHR
|
||||
add wave -noupdate -group Bpred -expand -group {branch update selection inputs} /testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/BPPredF
|
||||
add wave -noupdate -group Bpred -expand -group {branch update selection inputs} {/testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/InstrClassE[0]}
|
||||
@ -300,65 +300,65 @@ add wave -noupdate -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcac
|
||||
add wave -noupdate -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/SelAdrM
|
||||
add wave -noupdate -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/ReadDataBlockM
|
||||
add wave -noupdate -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/DCacheMemWriteData
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/MemWay[0]/WriteEnable}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/MemWay[0]/SetValid}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/MemWay[0]/SetDirty}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -label TAG {/testbench/dut/hart/lsu/dcache/MemWay[0]/CacheTagMem/StoredData}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/MemWay[0]/DirtyBits}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/MemWay[0]/ValidBits}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word0 {/testbench/dut/hart/lsu/dcache/MemWay[0]/word[0]/CacheDataMem/StoredData}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word0 {/testbench/dut/hart/lsu/dcache/MemWay[0]/word[0]/CacheDataMem/WriteEnable}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word1 {/testbench/dut/hart/lsu/dcache/MemWay[0]/word[1]/CacheDataMem/StoredData}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word1 {/testbench/dut/hart/lsu/dcache/MemWay[0]/word[1]/CacheDataMem/WriteEnable}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word2 {/testbench/dut/hart/lsu/dcache/MemWay[0]/word[2]/CacheDataMem/WriteEnable}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word2 {/testbench/dut/hart/lsu/dcache/MemWay[0]/word[2]/CacheDataMem/StoredData}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word3 {/testbench/dut/hart/lsu/dcache/MemWay[0]/word[3]/CacheDataMem/WriteEnable}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word3 {/testbench/dut/hart/lsu/dcache/MemWay[0]/word[3]/CacheDataMem/StoredData}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 {/testbench/dut/hart/lsu/dcache/MemWay[1]/DirtyBits}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 {/testbench/dut/hart/lsu/dcache/MemWay[1]/SetDirty}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 {/testbench/dut/hart/lsu/dcache/MemWay[1]/WriteEnable}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 {/testbench/dut/hart/lsu/dcache/MemWay[1]/WriteWordEnable}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -label TAG {/testbench/dut/hart/lsu/dcache/MemWay[1]/CacheTagMem/StoredData}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word0 {/testbench/dut/hart/lsu/dcache/MemWay[1]/word[0]/CacheDataMem/WriteEnable}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word0 {/testbench/dut/hart/lsu/dcache/MemWay[1]/word[0]/CacheDataMem/StoredData}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word1 {/testbench/dut/hart/lsu/dcache/MemWay[1]/word[1]/CacheDataMem/WriteEnable}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word1 {/testbench/dut/hart/lsu/dcache/MemWay[1]/word[1]/CacheDataMem/StoredData}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word2 {/testbench/dut/hart/lsu/dcache/MemWay[1]/word[2]/CacheDataMem/WriteEnable}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word2 {/testbench/dut/hart/lsu/dcache/MemWay[1]/word[2]/CacheDataMem/StoredData}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word3 {/testbench/dut/hart/lsu/dcache/MemWay[1]/word[3]/CacheDataMem/WriteEnable}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word3 {/testbench/dut/hart/lsu/dcache/MemWay[1]/word[3]/CacheDataMem/StoredData}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 {/testbench/dut/hart/lsu/dcache/MemWay[2]/WriteEnable}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 {/testbench/dut/hart/lsu/dcache/MemWay[2]/SetValid}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 {/testbench/dut/hart/lsu/dcache/MemWay[2]/SetDirty}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -label TAG {/testbench/dut/hart/lsu/dcache/MemWay[2]/CacheTagMem/StoredData}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 {/testbench/dut/hart/lsu/dcache/MemWay[2]/DirtyBits}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 {/testbench/dut/hart/lsu/dcache/MemWay[2]/ValidBits}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word0 {/testbench/dut/hart/lsu/dcache/MemWay[2]/word[0]/CacheDataMem/StoredData}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word0 {/testbench/dut/hart/lsu/dcache/MemWay[2]/word[0]/CacheDataMem/WriteEnable}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word1 {/testbench/dut/hart/lsu/dcache/MemWay[2]/word[1]/CacheDataMem/StoredData}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word1 {/testbench/dut/hart/lsu/dcache/MemWay[2]/word[1]/CacheDataMem/WriteEnable}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word2 {/testbench/dut/hart/lsu/dcache/MemWay[2]/word[2]/CacheDataMem/WriteEnable}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word2 {/testbench/dut/hart/lsu/dcache/MemWay[2]/word[2]/CacheDataMem/StoredData}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word3 {/testbench/dut/hart/lsu/dcache/MemWay[2]/word[3]/CacheDataMem/WriteEnable}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word3 {/testbench/dut/hart/lsu/dcache/MemWay[2]/word[3]/CacheDataMem/StoredData}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/hart/lsu/dcache/MemWay[3]/WriteEnable}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/hart/lsu/dcache/MemWay[3]/SetValid}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/hart/lsu/dcache/MemWay[3]/SetDirty}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -label TAG {/testbench/dut/hart/lsu/dcache/MemWay[3]/CacheTagMem/StoredData}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/hart/lsu/dcache/MemWay[3]/DirtyBits}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/hart/lsu/dcache/MemWay[3]/ValidBits}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word0 {/testbench/dut/hart/lsu/dcache/MemWay[3]/word[0]/CacheDataMem/StoredData}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word0 {/testbench/dut/hart/lsu/dcache/MemWay[3]/word[0]/CacheDataMem/WriteEnable}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word1 {/testbench/dut/hart/lsu/dcache/MemWay[3]/word[1]/CacheDataMem/StoredData}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word1 {/testbench/dut/hart/lsu/dcache/MemWay[3]/word[1]/CacheDataMem/WriteEnable}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word2 {/testbench/dut/hart/lsu/dcache/MemWay[3]/word[2]/CacheDataMem/WriteEnable}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word2 {/testbench/dut/hart/lsu/dcache/MemWay[3]/word[2]/CacheDataMem/StoredData}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word3 {/testbench/dut/hart/lsu/dcache/MemWay[3]/word[3]/CacheDataMem/WriteEnable}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word3 {/testbench/dut/hart/lsu/dcache/MemWay[3]/word[3]/CacheDataMem/StoredData}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group valid/dirty /testbench/dut/hart/lsu/dcache/SetValid
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group valid/dirty /testbench/dut/hart/lsu/dcache/ClearValid
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group valid/dirty /testbench/dut/hart/lsu/dcache/SetDirty
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group valid/dirty /testbench/dut/hart/lsu/dcache/ClearDirty
|
||||
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way0 {/testbench/dut/hart/lsu/dcache/MemWay[0]/WriteEnable}
|
||||
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way0 {/testbench/dut/hart/lsu/dcache/MemWay[0]/SetValid}
|
||||
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way0 {/testbench/dut/hart/lsu/dcache/MemWay[0]/SetDirty}
|
||||
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way0 -label TAG {/testbench/dut/hart/lsu/dcache/MemWay[0]/CacheTagMem/StoredData}
|
||||
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way0 {/testbench/dut/hart/lsu/dcache/MemWay[0]/DirtyBits}
|
||||
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way0 {/testbench/dut/hart/lsu/dcache/MemWay[0]/ValidBits}
|
||||
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way0 -expand -group Way0Word0 {/testbench/dut/hart/lsu/dcache/MemWay[0]/word[0]/CacheDataMem/StoredData}
|
||||
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way0 -expand -group Way0Word0 {/testbench/dut/hart/lsu/dcache/MemWay[0]/word[0]/CacheDataMem/WriteEnable}
|
||||
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way0 -expand -group Way0Word1 {/testbench/dut/hart/lsu/dcache/MemWay[0]/word[1]/CacheDataMem/StoredData}
|
||||
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way0 -expand -group Way0Word1 {/testbench/dut/hart/lsu/dcache/MemWay[0]/word[1]/CacheDataMem/WriteEnable}
|
||||
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way0 -expand -group Way0Word2 {/testbench/dut/hart/lsu/dcache/MemWay[0]/word[2]/CacheDataMem/WriteEnable}
|
||||
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way0 -expand -group Way0Word2 {/testbench/dut/hart/lsu/dcache/MemWay[0]/word[2]/CacheDataMem/StoredData}
|
||||
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way0 -expand -group Way0Word3 {/testbench/dut/hart/lsu/dcache/MemWay[0]/word[3]/CacheDataMem/WriteEnable}
|
||||
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way0 -expand -group Way0Word3 {/testbench/dut/hart/lsu/dcache/MemWay[0]/word[3]/CacheDataMem/StoredData}
|
||||
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way1 {/testbench/dut/hart/lsu/dcache/MemWay[1]/DirtyBits}
|
||||
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way1 {/testbench/dut/hart/lsu/dcache/MemWay[1]/SetDirty}
|
||||
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way1 {/testbench/dut/hart/lsu/dcache/MemWay[1]/WriteEnable}
|
||||
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way1 {/testbench/dut/hart/lsu/dcache/MemWay[1]/WriteWordEnable}
|
||||
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way1 -label TAG {/testbench/dut/hart/lsu/dcache/MemWay[1]/CacheTagMem/StoredData}
|
||||
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way1 -expand -group Way1Word0 {/testbench/dut/hart/lsu/dcache/MemWay[1]/word[0]/CacheDataMem/WriteEnable}
|
||||
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way1 -expand -group Way1Word0 {/testbench/dut/hart/lsu/dcache/MemWay[1]/word[0]/CacheDataMem/StoredData}
|
||||
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way1 -expand -group Way1Word1 {/testbench/dut/hart/lsu/dcache/MemWay[1]/word[1]/CacheDataMem/WriteEnable}
|
||||
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way1 -expand -group Way1Word1 {/testbench/dut/hart/lsu/dcache/MemWay[1]/word[1]/CacheDataMem/StoredData}
|
||||
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way1 -expand -group Way1Word2 {/testbench/dut/hart/lsu/dcache/MemWay[1]/word[2]/CacheDataMem/WriteEnable}
|
||||
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way1 -expand -group Way1Word2 {/testbench/dut/hart/lsu/dcache/MemWay[1]/word[2]/CacheDataMem/StoredData}
|
||||
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way1 -expand -group Way1Word3 {/testbench/dut/hart/lsu/dcache/MemWay[1]/word[3]/CacheDataMem/WriteEnable}
|
||||
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way1 -expand -group Way1Word3 {/testbench/dut/hart/lsu/dcache/MemWay[1]/word[3]/CacheDataMem/StoredData}
|
||||
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way2 {/testbench/dut/hart/lsu/dcache/MemWay[2]/WriteEnable}
|
||||
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way2 {/testbench/dut/hart/lsu/dcache/MemWay[2]/SetValid}
|
||||
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way2 {/testbench/dut/hart/lsu/dcache/MemWay[2]/SetDirty}
|
||||
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way2 -label TAG {/testbench/dut/hart/lsu/dcache/MemWay[2]/CacheTagMem/StoredData}
|
||||
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way2 {/testbench/dut/hart/lsu/dcache/MemWay[2]/DirtyBits}
|
||||
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way2 {/testbench/dut/hart/lsu/dcache/MemWay[2]/ValidBits}
|
||||
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way2 -expand -group Way2Word0 {/testbench/dut/hart/lsu/dcache/MemWay[2]/word[0]/CacheDataMem/StoredData}
|
||||
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way2 -expand -group Way2Word0 {/testbench/dut/hart/lsu/dcache/MemWay[2]/word[0]/CacheDataMem/WriteEnable}
|
||||
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way2 -expand -group Way2Word1 {/testbench/dut/hart/lsu/dcache/MemWay[2]/word[1]/CacheDataMem/StoredData}
|
||||
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way2 -expand -group Way2Word1 {/testbench/dut/hart/lsu/dcache/MemWay[2]/word[1]/CacheDataMem/WriteEnable}
|
||||
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way2 -expand -group Way2Word2 {/testbench/dut/hart/lsu/dcache/MemWay[2]/word[2]/CacheDataMem/WriteEnable}
|
||||
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way2 -expand -group Way2Word2 {/testbench/dut/hart/lsu/dcache/MemWay[2]/word[2]/CacheDataMem/StoredData}
|
||||
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way2 -expand -group Way2Word3 {/testbench/dut/hart/lsu/dcache/MemWay[2]/word[3]/CacheDataMem/WriteEnable}
|
||||
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way2 -expand -group Way2Word3 {/testbench/dut/hart/lsu/dcache/MemWay[2]/word[3]/CacheDataMem/StoredData}
|
||||
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way3 {/testbench/dut/hart/lsu/dcache/MemWay[3]/WriteEnable}
|
||||
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way3 {/testbench/dut/hart/lsu/dcache/MemWay[3]/SetValid}
|
||||
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way3 {/testbench/dut/hart/lsu/dcache/MemWay[3]/SetDirty}
|
||||
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way3 -label TAG {/testbench/dut/hart/lsu/dcache/MemWay[3]/CacheTagMem/StoredData}
|
||||
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way3 {/testbench/dut/hart/lsu/dcache/MemWay[3]/DirtyBits}
|
||||
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way3 {/testbench/dut/hart/lsu/dcache/MemWay[3]/ValidBits}
|
||||
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way3 -expand -group Way3Word0 {/testbench/dut/hart/lsu/dcache/MemWay[3]/word[0]/CacheDataMem/StoredData}
|
||||
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way3 -expand -group Way3Word0 {/testbench/dut/hart/lsu/dcache/MemWay[3]/word[0]/CacheDataMem/WriteEnable}
|
||||
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way3 -expand -group Way3Word1 {/testbench/dut/hart/lsu/dcache/MemWay[3]/word[1]/CacheDataMem/StoredData}
|
||||
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way3 -expand -group Way3Word1 {/testbench/dut/hart/lsu/dcache/MemWay[3]/word[1]/CacheDataMem/WriteEnable}
|
||||
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way3 -expand -group Way3Word2 {/testbench/dut/hart/lsu/dcache/MemWay[3]/word[2]/CacheDataMem/WriteEnable}
|
||||
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way3 -expand -group Way3Word2 {/testbench/dut/hart/lsu/dcache/MemWay[3]/word[2]/CacheDataMem/StoredData}
|
||||
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way3 -expand -group Way3Word3 {/testbench/dut/hart/lsu/dcache/MemWay[3]/word[3]/CacheDataMem/WriteEnable}
|
||||
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way3 -expand -group Way3Word3 {/testbench/dut/hart/lsu/dcache/MemWay[3]/word[3]/CacheDataMem/StoredData}
|
||||
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group valid/dirty /testbench/dut/hart/lsu/dcache/SetValid
|
||||
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group valid/dirty /testbench/dut/hart/lsu/dcache/ClearValid
|
||||
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group valid/dirty /testbench/dut/hart/lsu/dcache/SetDirty
|
||||
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group valid/dirty /testbench/dut/hart/lsu/dcache/ClearDirty
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way0 {/testbench/dut/hart/lsu/dcache/MemWay[0]/WayHit}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way0 {/testbench/dut/hart/lsu/dcache/MemWay[0]/Valid}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way0 {/testbench/dut/hart/lsu/dcache/MemWay[0]/Dirty}
|
||||
@ -383,17 +383,17 @@ add wave -noupdate -group lsu -expand -group dcache -group Victim /testbench/dut
|
||||
add wave -noupdate -group lsu -expand -group dcache -group Victim /testbench/dut/hart/lsu/dcache/VictimWay
|
||||
add wave -noupdate -group lsu -expand -group dcache -group Victim /testbench/dut/hart/lsu/dcache/VictimDirtyWay
|
||||
add wave -noupdate -group lsu -expand -group dcache -group Victim /testbench/dut/hart/lsu/dcache/VictimDirty
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {CPU side} /testbench/dut/hart/lsu/dcache/MemRWM
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {CPU side} /testbench/dut/hart/lsu/dcache/MemAdrE
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {CPU side} /testbench/dut/hart/lsu/dcache/MemPAdrM
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {CPU side} /testbench/dut/hart/lsu/dcache/Funct3M
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {CPU side} /testbench/dut/hart/lsu/dcache/Funct7M
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {CPU side} /testbench/dut/hart/lsu/dcache/AtomicM
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {CPU side} /testbench/dut/hart/lsu/dcache/FlushDCacheM
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {CPU side} /testbench/dut/hart/lsu/dcache/CacheableM
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {CPU side} /testbench/dut/hart/lsu/dcache/WriteDataM
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {CPU side} /testbench/dut/hart/lsu/dcache/ReadDataM
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {CPU side} /testbench/dut/hart/lsu/dcache/DCacheStall
|
||||
add wave -noupdate -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/MemRWM
|
||||
add wave -noupdate -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/MemAdrE
|
||||
add wave -noupdate -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/MemPAdrM
|
||||
add wave -noupdate -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/Funct3M
|
||||
add wave -noupdate -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/Funct7M
|
||||
add wave -noupdate -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/AtomicM
|
||||
add wave -noupdate -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/FlushDCacheM
|
||||
add wave -noupdate -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/CacheableM
|
||||
add wave -noupdate -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/WriteDataM
|
||||
add wave -noupdate -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/ReadDataM
|
||||
add wave -noupdate -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/DCacheStall
|
||||
add wave -noupdate -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/FlushAdrFlag
|
||||
add wave -noupdate -group lsu -expand -group dcache -group status /testbench/dut/hart/lsu/dcache/WayHit
|
||||
add wave -noupdate -group lsu -expand -group dcache -group status -color {Medium Orchid} /testbench/dut/hart/lsu/dcache/CacheHit
|
||||
@ -519,12 +519,29 @@ add wave -noupdate -group UART /testbench/dut/uncore/uart/uart/HWDATA
|
||||
add wave -noupdate -expand -group SDC -color Gold -label {AHBLite FSM} /testbench/dut/uncore/sdc/SDC/CurrState
|
||||
add wave -noupdate -expand -group SDC /testbench/dut/uncore/sdc/SDC/HCLK
|
||||
add wave -noupdate -expand -group SDC /testbench/dut/uncore/sdc/SDC/CLKGate
|
||||
add wave -noupdate -expand -group SDC /testbench/dut/uncore/sdc/SDC/SDCCLKIn
|
||||
add wave -noupdate -expand -group SDC /testbench/dut/uncore/sdc/SDC/SDCCLK
|
||||
add wave -noupdate -expand -group SDC -color Gold -label {cmd fsm} /testbench/dut/uncore/sdc/SDC/sd_top/my_sd_cmd_fsm/r_curr_state
|
||||
add wave -noupdate -expand -group SDC -color Gold -label {dat fsm} /testbench/dut/uncore/sdc/SDC/sd_top/my_sd_dat_fsm/r_curr_state
|
||||
add wave -noupdate -expand -group SDC -color Gold -label {clk fsm} /testbench/dut/uncore/sdc/SDC/sd_top/my_clk_fsm/r_curr_state
|
||||
add wave -noupdate -expand -group SDC -expand -group registers /testbench/dut/uncore/sdc/SDC/CLKDiv
|
||||
add wave -noupdate -expand -group SDC -expand -group registers /testbench/dut/uncore/sdc/SDC/Command
|
||||
add wave -noupdate -expand -group SDC -expand -group registers /testbench/dut/uncore/sdc/SDC/Address
|
||||
add wave -noupdate -expand -group SDC -group {AHBLite interface} -color Aquamarine /testbench/dut/uncore/sdc/SDC/HSELSDC
|
||||
add wave -noupdate -expand -group SDC -group {AHBLite interface} /testbench/dut/uncore/sdc/SDC/HADDR
|
||||
add wave -noupdate -expand -group SDC -group {AHBLite interface} /testbench/dut/uncore/sdc/SDC/HWRITE
|
||||
add wave -noupdate -expand -group SDC -group {AHBLite interface} /testbench/dut/uncore/sdc/SDC/HREADY
|
||||
add wave -noupdate -expand -group SDC -group {AHBLite interface} /testbench/dut/uncore/sdc/SDC/HTRANS
|
||||
add wave -noupdate -expand -group SDC -group {AHBLite interface} /testbench/dut/uncore/sdc/SDC/HWDATA
|
||||
add wave -noupdate -expand -group SDC -group {AHBLite interface} /testbench/dut/uncore/sdc/SDC/HREADSDC
|
||||
add wave -noupdate -expand -group SDC -group {AHBLite interface} /testbench/dut/uncore/sdc/SDC/HRESPSDC
|
||||
add wave -noupdate -expand -group SDC -group {AHBLite interface} /testbench/dut/uncore/sdc/SDC/HREADYSDC
|
||||
add wave -noupdate /testbench/dut/uncore/sdc/SDC/SDCReady
|
||||
add wave -noupdate /testbench/dut/hart/lsu/dmmu/pmachecker/adrdecs/sdcdec/PhysicalAddress
|
||||
add wave -noupdate /testbench/dut/hart/lsu/dmmu/pmachecker/adrdecs/sdcdec/Base
|
||||
add wave -noupdate /testbench/dut/hart/lsu/dmmu/pmachecker/adrdecs/sdcdec/Range
|
||||
TreeUpdate [SetDefaultTree]
|
||||
WaveRestoreCursors {{Cursor 6} {1776925 ns} 0}
|
||||
WaveRestoreCursors {{Cursor 6} {1256 ns} 0} {{Cursor 2} {7326252 ns} 0}
|
||||
quietly wave cursor active 1
|
||||
configure wave -namecolwidth 250
|
||||
configure wave -valuecolwidth 297
|
||||
@ -540,4 +557,4 @@ configure wave -griddelta 40
|
||||
configure wave -timeline 0
|
||||
configure wave -timelineunits ns
|
||||
update
|
||||
WaveRestoreZoom {1773973 ns} {1779877 ns}
|
||||
WaveRestoreZoom {1219 ns} {1331 ns}
|
||||
|
||||
@ -41,7 +41,7 @@ module adrdecs (
|
||||
adrdec gpiodec(PhysicalAddress, `GPIO_BASE, `GPIO_RANGE, `GPIO_SUPPORTED, AccessRW, Size, 4'b0100, SelRegions[3]);
|
||||
adrdec uartdec(PhysicalAddress, `UART_BASE, `UART_RANGE, `UART_SUPPORTED, AccessRW, Size, 4'b0001, SelRegions[2]);
|
||||
adrdec plicdec(PhysicalAddress, `PLIC_BASE, `PLIC_RANGE, `PLIC_SUPPORTED, AccessRW, Size, 4'b0100, SelRegions[1]);
|
||||
adrdec sdcdec(PhysicalAddress, `SDC_BASE, `SDC_RANGE, `SDC_SUPPORTED, AccessRW, Size, 4'b0011, SelRegions[0]);
|
||||
adrdec sdcdec(PhysicalAddress, `SDC_BASE, `SDC_RANGE, `SDC_SUPPORTED, AccessRW, Size, 4'b1100, SelRegions[0]);
|
||||
|
||||
assign SelRegions[7] = ~|(SelRegions[6:0]);
|
||||
|
||||
|
||||
@ -25,7 +25,7 @@
|
||||
|
||||
`include "wally-config.vh"
|
||||
|
||||
`define SDCCLKDIV 8'd2
|
||||
`define SDCCLKDIV -8'd2
|
||||
|
||||
module SDC
|
||||
(input logic HCLK,
|
||||
@ -69,7 +69,6 @@ module SDC
|
||||
logic [2:0] ErrorCode;
|
||||
logic InvalidCommand;
|
||||
logic Done;
|
||||
logic Busy;
|
||||
|
||||
logic StartCLKDivUpdate;
|
||||
logic CLKDivUpdateEn;
|
||||
@ -80,14 +79,21 @@ module SDC
|
||||
|
||||
logic SDCDataValid;
|
||||
logic [`XLEN-1:0] SDCReadData;
|
||||
logic [`XLEN-1:0] ReadData;
|
||||
logic [`XLEN-1:0] SDCWriteData;
|
||||
logic FatalError;
|
||||
|
||||
logic [4095:0] ReadData512Byte;
|
||||
logic [`XLEN-1:0] ReadData512ByteWords [4096/`XLEN-1:0] ;
|
||||
logic SDCReady;
|
||||
logic SDCRestarting;
|
||||
logic SDCLast;
|
||||
|
||||
logic [$clog2(4096/`XLEN)-1:0] WordCount;
|
||||
logic WordCountRst;
|
||||
|
||||
|
||||
genvar index;
|
||||
|
||||
|
||||
// registers
|
||||
//| Offset | Name | Size | Purpose |
|
||||
@ -154,36 +160,52 @@ module SDC
|
||||
end
|
||||
endgenerate
|
||||
|
||||
flopen #(`XLEN) DataReg(HCLK, (HADDRDelay == 'h18 & RegWrite) | (SDCDataValid),
|
||||
SDCDataValid ? SDCReadData : HWDATA, ReadData);
|
||||
flopen #(`XLEN) DataReg(HCLK, (HADDRDelay == 'h18 & RegWrite),
|
||||
HWDATA, SDCWriteData);
|
||||
|
||||
generate
|
||||
if(`XLEN == 64) begin
|
||||
always_comb
|
||||
case(HADDRDelay[4:0])
|
||||
'h0: HREADSDC = {56'b0, CLKDiv};
|
||||
'h4: HREADSDC = {58'b0, ErrorCode, InvalidCommand, Done, Busy};
|
||||
'h4: HREADSDC = {58'b0, ErrorCode, InvalidCommand, Done, ~SDCReady};
|
||||
'h8: HREADSDC = {61'b0, Command};
|
||||
'hC: HREADSDC = 'h200;
|
||||
'h10: HREADSDC = {Address, 9'b0};
|
||||
'h18: HREADSDC = ReadData;
|
||||
'h18: HREADSDC = SDCReadData;
|
||||
default: HREADSDC = {56'b0, CLKDiv};
|
||||
endcase
|
||||
endcase // case (HADDRDelay[4:0])
|
||||
end else begin
|
||||
always_comb
|
||||
case(HADDRDelay[4:0])
|
||||
'h0: HREADSDC = {24'b0, CLKDiv};
|
||||
'h4: HREADSDC = {26'b0, ErrorCode, InvalidCommand, Done, Busy};
|
||||
'h4: HREADSDC = {26'b0, ErrorCode, InvalidCommand, Done, ~SDCReady};
|
||||
'h8: HREADSDC = {29'b0, Command};
|
||||
'hC: HREADSDC = 'h200;
|
||||
'h10: HREADSDC = {Address[31:9], 9'b0};
|
||||
'h14: HREADSDC = Address[63:32];
|
||||
'h18: HREADSDC = ReadData[31:0];
|
||||
'h18: HREADSDC = SDCReadData[31:0];
|
||||
default: HREADSDC = {24'b0, CLKDiv};
|
||||
endcase
|
||||
end
|
||||
endgenerate
|
||||
|
||||
|
||||
for(index = 0; index < 4096/`XLEN; index++) begin
|
||||
assign ReadData512ByteWords[index] = ReadData512Byte[(index+1)*`XLEN-1:index*`XLEN];
|
||||
end
|
||||
|
||||
assign SDCReadData = ReadData512ByteWords[WordCount];
|
||||
|
||||
flopenr #($clog2(4096/`XLEN)) WordCountReg
|
||||
(.clk(HCLK),
|
||||
.reset(~HRESETn | WordCountRst),
|
||||
.en(HADDRDelay[4:0] == 'h18 & HREADYSDC),
|
||||
.d(WordCount + 1'b1),
|
||||
.q(WordCount));
|
||||
|
||||
|
||||
|
||||
typedef enum {STATE_READY,
|
||||
|
||||
// clock update states
|
||||
@ -196,7 +218,9 @@ module SDC
|
||||
STATE_RESTART,
|
||||
|
||||
// SDC operation
|
||||
STATE_PROCESS_CMD
|
||||
STATE_PROCESS_CMD,
|
||||
|
||||
STATE_READ
|
||||
} statetype;
|
||||
|
||||
|
||||
@ -210,16 +234,19 @@ module SDC
|
||||
CLKDivUpdateEn = 1'b0;
|
||||
HREADYSDC = 1'b0;
|
||||
SDCCLKEN = 1'b1;
|
||||
WordCountRst = 1'b0;
|
||||
case (CurrState)
|
||||
|
||||
STATE_READY : begin
|
||||
if (StartCLKDivUpdate)begin
|
||||
NextState = STATE_CLK_DIV1;
|
||||
HREADYSDC = 1'b0;
|
||||
/* -----\/----- EXCLUDED -----\/-----
|
||||
end else if () begin
|
||||
-----/\----- EXCLUDED -----/\----- */
|
||||
|
||||
end else if (Command[2] | Command[1]) begin
|
||||
NextState = STATE_PROCESS_CMD;
|
||||
HREADYSDC = 1'b0;
|
||||
end else if(HADDRDelay[4:0] == 'h18) begin
|
||||
NextState = STATE_READ;
|
||||
HREADYSDC = 1'b0;
|
||||
end else begin
|
||||
NextState = STATE_READY;
|
||||
HREADYSDC = 1'b1;
|
||||
@ -241,6 +268,19 @@ module SDC
|
||||
STATE_CLK_DIV4: begin
|
||||
NextState = STATE_READY;
|
||||
end
|
||||
STATE_PROCESS_CMD: begin
|
||||
HREADYSDC = 1'b1;
|
||||
WordCountRst = 1'b1;
|
||||
if(SDCDataValid) begin
|
||||
NextState = STATE_READY;
|
||||
end else begin
|
||||
NextState = STATE_PROCESS_CMD;
|
||||
end
|
||||
end
|
||||
STATE_READ: begin
|
||||
NextState = STATE_READY;
|
||||
HREADYSDC = 1'b1;
|
||||
end
|
||||
endcase
|
||||
end
|
||||
|
||||
@ -255,7 +295,7 @@ module SDC
|
||||
clkdivider #(8) clkdivider(.i_COUNT_IN_MAX(CLKDiv),
|
||||
.i_EN(CLKDiv != 'b1),
|
||||
.i_CLK(CLKGate),
|
||||
.i_RST(~HRESETn),
|
||||
.i_RST(~HRESETn | CLKDivUpdateEn),
|
||||
.o_CLK(SDCCLKIn));
|
||||
|
||||
sd_top sd_top(.CLK(SDCCLKIn),
|
||||
@ -278,6 +318,13 @@ module SDC
|
||||
.i_COUNT_IN_MAX(-8'd62),
|
||||
.LIMIT_SD_TIMERS(1'b1)); // *** must change this to 0 for real hardware.
|
||||
|
||||
/* -----\/----- EXCLUDED -----\/-----
|
||||
flopenr #(1) DoneReg(.clk(HCLK),
|
||||
.reset(~HRESETn),
|
||||
.en(SDCDataValid | Command[2]),
|
||||
.d(SDCDataValid ? 1'b1 :
|
||||
-----/\----- EXCLUDED -----/\----- */
|
||||
|
||||
|
||||
|
||||
endmodule
|
||||
|
||||
@ -621,7 +621,7 @@ string tests32f[] = '{
|
||||
-----/\----- EXCLUDED -----/\----- */
|
||||
// read test vectors into memory
|
||||
memfilename = {"../../imperas-riscv-tests/work/", tests[test], ".elf.memfile"};
|
||||
romfilename = {"../../imperas-riscv-tests/work/rv64BP/blink-led.memfile"};
|
||||
romfilename = {"../../imperas-riscv-tests/work/rv64BP/fpga-test-sdc.memfile"};
|
||||
$readmemh(memfilename, dut.uncore.dtim.RAM);
|
||||
$readmemh(romfilename, dut.uncore.bootdtim.bootdtim.RAM);
|
||||
ProgramAddrMapFile = {"../../imperas-riscv-tests/work/", tests[test], ".elf.objdump.addr"};
|
||||
|
||||
Loading…
Reference in New Issue
Block a user