forked from Github_Repos/cvw
Refactored stalls and flushes, including FDIV flush with FlushE
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5b040b7935
commit
4365c99b52
@ -161,9 +161,9 @@ def main():
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os.mkdir("logs")
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os.mkdir("logs")
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#print(os.getcwd())
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#print(os.getcwd())
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#print(regressionDir)
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#print(regressionDir)
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shutil.rmtree("wkdir")
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except:
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except:
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pass
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pass
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shutil.rmtree("wkdir")
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os.mkdir("wkdir")
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os.mkdir("wkdir")
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if '-makeTests' in sys.argv:
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if '-makeTests' in sys.argv:
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4
pipelined/regression/wkdir/.gitignore
vendored
4
pipelined/regression/wkdir/.gitignore
vendored
@ -1,4 +0,0 @@
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# Ignore everything in this directory
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*
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# Except this file
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!.gitignore
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@ -43,7 +43,7 @@ module fdivsqrt(
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input logic FDivStartE, IDivStartE,
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input logic FDivStartE, IDivStartE,
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input logic StallM,
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input logic StallM,
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input logic StallE,
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input logic StallE,
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input logic TrapM,
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input logic FlushE,
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input logic SqrtE, SqrtM,
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input logic SqrtE, SqrtM,
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input logic [`XLEN-1:0] ForwardedSrcAE, ForwardedSrcBE, // *** these are the src outputs before the mux choosing between them and PCE to put in srcA/B
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input logic [`XLEN-1:0] ForwardedSrcAE, ForwardedSrcBE, // *** these are the src outputs before the mux choosing between them and PCE to put in srcA/B
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input logic [2:0] Funct3E, Funct3M,
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input logic [2:0] Funct3E, Funct3M,
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@ -77,7 +77,7 @@ module fdivsqrt(
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.ForwardedSrcAE, .ForwardedSrcBE, .Funct3E, .Funct3M, .MDUE, .W64E);
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.ForwardedSrcAE, .ForwardedSrcBE, .Funct3E, .Funct3M, .MDUE, .W64E);
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fdivsqrtfsm fdivsqrtfsm(
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fdivsqrtfsm fdivsqrtfsm(
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.clk, .reset, .FmtE, .XsE, .SqrtE,
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.clk, .reset, .FmtE, .XsE, .SqrtE,
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.FDivBusyE, .FDivStartE, .IDivStartE, .IFDivStartE, .FDivDoneE, .StallE, .StallM, .TrapM, /*.DivDone, */ .XZeroE, .YZeroE,
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.FDivBusyE, .FDivStartE, .IDivStartE, .IFDivStartE, .FDivDoneE, .StallE, .StallM, .FlushE, /*.DivDone, */ .XZeroE, .YZeroE,
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.XNaNE, .YNaNE, .MDUE, .n,
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.XNaNE, .YNaNE, .MDUE, .n,
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.XInfE, .YInfE, .WZero, .SpecialCaseM);
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.XInfE, .YInfE, .WZero, .SpecialCaseM);
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fdivsqrtiter fdivsqrtiter(
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fdivsqrtiter fdivsqrtiter(
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@ -42,7 +42,7 @@ module fdivsqrtfsm(
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input logic SqrtE,
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input logic SqrtE,
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input logic StallE,
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input logic StallE,
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input logic StallM,
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input logic StallM,
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input logic TrapM,
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input logic FlushE,
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input logic WZero,
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input logic WZero,
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input logic MDUE,
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input logic MDUE,
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input logic [`DIVBLEN:0] n,
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input logic [`DIVBLEN:0] n,
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@ -107,7 +107,7 @@ module fdivsqrtfsm(
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/* verilator lint_on WIDTH */
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/* verilator lint_on WIDTH */
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always_ff @(posedge clk) begin
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always_ff @(posedge clk) begin
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if (reset | TrapM) begin
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if (reset | FlushE) begin
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state <= #1 IDLE;
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state <= #1 IDLE;
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end else if (IFDivStartE) begin
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end else if (IFDivStartE) begin
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step <= cycles;
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step <= cycles;
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@ -38,7 +38,7 @@ module fpu (
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input logic [`FLEN-1:0] ReadDataW, // Read data (from LSU)
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input logic [`FLEN-1:0] ReadDataW, // Read data (from LSU)
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input logic [`XLEN-1:0] ForwardedSrcAE, ForwardedSrcBE, // Integer input (from IEU)
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input logic [`XLEN-1:0] ForwardedSrcAE, ForwardedSrcBE, // Integer input (from IEU)
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input logic StallE, StallM, StallW, // stall signals (from HZU)
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input logic StallE, StallM, StallW, // stall signals (from HZU)
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input logic TrapM,
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//input logic TrapM,
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input logic FlushE, FlushM, FlushW, // flush signals (from HZU)
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input logic FlushE, FlushM, FlushW, // flush signals (from HZU)
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input logic [4:0] RdM, RdW, // which FP register to write to (from IEU)
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input logic [4:0] RdM, RdW, // which FP register to write to (from IEU)
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input logic [1:0] STATUS_FS, // Is floating-point enabled? (From privileged unit)
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input logic [1:0] STATUS_FS, // Is floating-point enabled? (From privileged unit)
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@ -268,7 +268,7 @@ module fpu (
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fdivsqrt fdivsqrt(.clk, .reset, .FmtE, .XmE, .YmE, .XeE, .YeE, .SqrtE(OpCtrlE[0]), .SqrtM(OpCtrlM[0]),
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fdivsqrt fdivsqrt(.clk, .reset, .FmtE, .XmE, .YmE, .XeE, .YeE, .SqrtE(OpCtrlE[0]), .SqrtM(OpCtrlM[0]),
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.XInfE, .YInfE, .XZeroE, .YZeroE, .XNaNE, .YNaNE, .FDivStartE, .IDivStartE, .XsE,
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.XInfE, .YInfE, .XZeroE, .YZeroE, .XNaNE, .YNaNE, .FDivStartE, .IDivStartE, .XsE,
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.ForwardedSrcAE, .ForwardedSrcBE, .Funct3E, .Funct3M, .MDUE, .W64E,
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.ForwardedSrcAE, .ForwardedSrcBE, .Funct3E, .Funct3M, .MDUE, .W64E,
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.StallE, .StallM, .TrapM, .DivSM, .FDivBusyE, .IFDivStartE, .FDivDoneE, .QeM,
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.StallE, .StallM, .FlushE, .DivSM, .FDivBusyE, .IFDivStartE, .FDivDoneE, .QeM,
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.QmM, .FPIntDivResultM /*, .DivDone(DivDoneM) */);
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.QmM, .FPIntDivResultM /*, .DivDone(DivDoneM) */);
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//
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//
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@ -62,7 +62,7 @@ module hazard(
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// If any stages are stalled, the first stage that isn't stalled must flush.
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// If any stages are stalled, the first stage that isn't stalled must flush.
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assign FlushDCause = TrapM | RetM | BPPredWrongE | CSRWriteFenceM;
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assign FlushDCause = TrapM | RetM | BPPredWrongE | CSRWriteFenceM;
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assign FlushECause = TrapM | RetM | BPPredWrongE | CSRWriteFenceM;
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assign FlushECause = TrapM | RetM | (BPPredWrongE & ~(DivBusyE | FDivBusyE)) | CSRWriteFenceM;
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assign FlushMCause = TrapM | RetM | CSRWriteFenceM;
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assign FlushMCause = TrapM | RetM | CSRWriteFenceM;
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// on Trap the memory stage should be flushed going into the W stage,
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// on Trap the memory stage should be flushed going into the W stage,
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// except if the instruction causing the Trap is an ecall or ebreak.
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// except if the instruction causing the Trap is an ecall or ebreak.
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@ -70,11 +70,11 @@ module hazard(
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assign StallFCause = '0;
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assign StallFCause = '0;
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// stall in decode if instruction is a load/mul/csr dependent on previous
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// stall in decode if instruction is a load/mul/csr dependent on previous
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assign StallDCause = (LoadStallD | StoreStallD | MDUStallD | CSRRdStallD | FCvtIntStallD | FStallD) & ~(FlushDCause);
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assign StallDCause = (LoadStallD | StoreStallD | MDUStallD | CSRRdStallD | FCvtIntStallD | FStallD) & ~FlushDCause;
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assign StallECause = (DivBusyE | FDivBusyE) & ~(TrapM | CSRWriteFenceM); // *** can we move to decode stage (KP?)
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assign StallECause = (DivBusyE | FDivBusyE) & ~FlushECause;
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// WFI terminates if any enabled interrupt is pending, even if global interrupts are disabled. It could also terminate with TW trap
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// WFI terminates if any enabled interrupt is pending, even if global interrupts are disabled. It could also terminate with TW trap
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assign StallMCause = ((wfiM) & (~TrapM & ~IntPendingM));
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assign StallMCause = ((wfiM) & (~TrapM & ~IntPendingM));
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assign StallWCause = ((IFUStallF | LSUStallM) & ~TrapM); // | (FDivBusyE & ~TrapM & ~IntPendingM);
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assign StallWCause = (IFUStallF | LSUStallM) & ~TrapM;
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assign #1 StallF = StallFCause | StallD;
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assign #1 StallF = StallFCause | StallD;
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assign #1 StallD = StallDCause | StallE;
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assign #1 StallD = StallDCause | StallE;
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@ -390,7 +390,7 @@ module wallypipelinedcore (
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.ReadDataW(ReadDataW[`FLEN-1:0]),// Read data from memory
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.ReadDataW(ReadDataW[`FLEN-1:0]),// Read data from memory
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.ForwardedSrcAE, // Integer input being processed (from IEU)
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.ForwardedSrcAE, // Integer input being processed (from IEU)
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.StallE, .StallM, .StallW, // stall signals from HZU
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.StallE, .StallM, .StallW, // stall signals from HZU
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.TrapM,
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//.TrapM,
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.FlushE, .FlushM, .FlushW, // flush signals from HZU
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.FlushE, .FlushM, .FlushW, // flush signals from HZU
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.RdM, .RdW, // which FP register to write to (from IEU)
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.RdM, .RdW, // which FP register to write to (from IEU)
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.STATUS_FS, // is floating-point enabled?
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.STATUS_FS, // is floating-point enabled?
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