Refactored stalls and flushes, including FDIV flush with FlushE

This commit is contained in:
David Harris 2022-12-15 10:56:18 -08:00
parent 5b040b7935
commit 4365c99b52
7 changed files with 12 additions and 16 deletions

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@ -161,9 +161,9 @@ def main():
os.mkdir("logs") os.mkdir("logs")
#print(os.getcwd()) #print(os.getcwd())
#print(regressionDir) #print(regressionDir)
shutil.rmtree("wkdir")
except: except:
pass pass
shutil.rmtree("wkdir")
os.mkdir("wkdir") os.mkdir("wkdir")
if '-makeTests' in sys.argv: if '-makeTests' in sys.argv:

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@ -1,4 +0,0 @@
# Ignore everything in this directory
*
# Except this file
!.gitignore

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@ -43,7 +43,7 @@ module fdivsqrt(
input logic FDivStartE, IDivStartE, input logic FDivStartE, IDivStartE,
input logic StallM, input logic StallM,
input logic StallE, input logic StallE,
input logic TrapM, input logic FlushE,
input logic SqrtE, SqrtM, input logic SqrtE, SqrtM,
input logic [`XLEN-1:0] ForwardedSrcAE, ForwardedSrcBE, // *** these are the src outputs before the mux choosing between them and PCE to put in srcA/B input logic [`XLEN-1:0] ForwardedSrcAE, ForwardedSrcBE, // *** these are the src outputs before the mux choosing between them and PCE to put in srcA/B
input logic [2:0] Funct3E, Funct3M, input logic [2:0] Funct3E, Funct3M,
@ -77,7 +77,7 @@ module fdivsqrt(
.ForwardedSrcAE, .ForwardedSrcBE, .Funct3E, .Funct3M, .MDUE, .W64E); .ForwardedSrcAE, .ForwardedSrcBE, .Funct3E, .Funct3M, .MDUE, .W64E);
fdivsqrtfsm fdivsqrtfsm( fdivsqrtfsm fdivsqrtfsm(
.clk, .reset, .FmtE, .XsE, .SqrtE, .clk, .reset, .FmtE, .XsE, .SqrtE,
.FDivBusyE, .FDivStartE, .IDivStartE, .IFDivStartE, .FDivDoneE, .StallE, .StallM, .TrapM, /*.DivDone, */ .XZeroE, .YZeroE, .FDivBusyE, .FDivStartE, .IDivStartE, .IFDivStartE, .FDivDoneE, .StallE, .StallM, .FlushE, /*.DivDone, */ .XZeroE, .YZeroE,
.XNaNE, .YNaNE, .MDUE, .n, .XNaNE, .YNaNE, .MDUE, .n,
.XInfE, .YInfE, .WZero, .SpecialCaseM); .XInfE, .YInfE, .WZero, .SpecialCaseM);
fdivsqrtiter fdivsqrtiter( fdivsqrtiter fdivsqrtiter(

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@ -42,7 +42,7 @@ module fdivsqrtfsm(
input logic SqrtE, input logic SqrtE,
input logic StallE, input logic StallE,
input logic StallM, input logic StallM,
input logic TrapM, input logic FlushE,
input logic WZero, input logic WZero,
input logic MDUE, input logic MDUE,
input logic [`DIVBLEN:0] n, input logic [`DIVBLEN:0] n,
@ -107,7 +107,7 @@ module fdivsqrtfsm(
/* verilator lint_on WIDTH */ /* verilator lint_on WIDTH */
always_ff @(posedge clk) begin always_ff @(posedge clk) begin
if (reset | TrapM) begin if (reset | FlushE) begin
state <= #1 IDLE; state <= #1 IDLE;
end else if (IFDivStartE) begin end else if (IFDivStartE) begin
step <= cycles; step <= cycles;

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@ -38,7 +38,7 @@ module fpu (
input logic [`FLEN-1:0] ReadDataW, // Read data (from LSU) input logic [`FLEN-1:0] ReadDataW, // Read data (from LSU)
input logic [`XLEN-1:0] ForwardedSrcAE, ForwardedSrcBE, // Integer input (from IEU) input logic [`XLEN-1:0] ForwardedSrcAE, ForwardedSrcBE, // Integer input (from IEU)
input logic StallE, StallM, StallW, // stall signals (from HZU) input logic StallE, StallM, StallW, // stall signals (from HZU)
input logic TrapM, //input logic TrapM,
input logic FlushE, FlushM, FlushW, // flush signals (from HZU) input logic FlushE, FlushM, FlushW, // flush signals (from HZU)
input logic [4:0] RdM, RdW, // which FP register to write to (from IEU) input logic [4:0] RdM, RdW, // which FP register to write to (from IEU)
input logic [1:0] STATUS_FS, // Is floating-point enabled? (From privileged unit) input logic [1:0] STATUS_FS, // Is floating-point enabled? (From privileged unit)
@ -268,7 +268,7 @@ module fpu (
fdivsqrt fdivsqrt(.clk, .reset, .FmtE, .XmE, .YmE, .XeE, .YeE, .SqrtE(OpCtrlE[0]), .SqrtM(OpCtrlM[0]), fdivsqrt fdivsqrt(.clk, .reset, .FmtE, .XmE, .YmE, .XeE, .YeE, .SqrtE(OpCtrlE[0]), .SqrtM(OpCtrlM[0]),
.XInfE, .YInfE, .XZeroE, .YZeroE, .XNaNE, .YNaNE, .FDivStartE, .IDivStartE, .XsE, .XInfE, .YInfE, .XZeroE, .YZeroE, .XNaNE, .YNaNE, .FDivStartE, .IDivStartE, .XsE,
.ForwardedSrcAE, .ForwardedSrcBE, .Funct3E, .Funct3M, .MDUE, .W64E, .ForwardedSrcAE, .ForwardedSrcBE, .Funct3E, .Funct3M, .MDUE, .W64E,
.StallE, .StallM, .TrapM, .DivSM, .FDivBusyE, .IFDivStartE, .FDivDoneE, .QeM, .StallE, .StallM, .FlushE, .DivSM, .FDivBusyE, .IFDivStartE, .FDivDoneE, .QeM,
.QmM, .FPIntDivResultM /*, .DivDone(DivDoneM) */); .QmM, .FPIntDivResultM /*, .DivDone(DivDoneM) */);
// //

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@ -62,7 +62,7 @@ module hazard(
// If any stages are stalled, the first stage that isn't stalled must flush. // If any stages are stalled, the first stage that isn't stalled must flush.
assign FlushDCause = TrapM | RetM | BPPredWrongE | CSRWriteFenceM; assign FlushDCause = TrapM | RetM | BPPredWrongE | CSRWriteFenceM;
assign FlushECause = TrapM | RetM | BPPredWrongE | CSRWriteFenceM; assign FlushECause = TrapM | RetM | (BPPredWrongE & ~(DivBusyE | FDivBusyE)) | CSRWriteFenceM;
assign FlushMCause = TrapM | RetM | CSRWriteFenceM; assign FlushMCause = TrapM | RetM | CSRWriteFenceM;
// on Trap the memory stage should be flushed going into the W stage, // on Trap the memory stage should be flushed going into the W stage,
// except if the instruction causing the Trap is an ecall or ebreak. // except if the instruction causing the Trap is an ecall or ebreak.
@ -70,11 +70,11 @@ module hazard(
assign StallFCause = '0; assign StallFCause = '0;
// stall in decode if instruction is a load/mul/csr dependent on previous // stall in decode if instruction is a load/mul/csr dependent on previous
assign StallDCause = (LoadStallD | StoreStallD | MDUStallD | CSRRdStallD | FCvtIntStallD | FStallD) & ~(FlushDCause); assign StallDCause = (LoadStallD | StoreStallD | MDUStallD | CSRRdStallD | FCvtIntStallD | FStallD) & ~FlushDCause;
assign StallECause = (DivBusyE | FDivBusyE) & ~(TrapM | CSRWriteFenceM); // *** can we move to decode stage (KP?) assign StallECause = (DivBusyE | FDivBusyE) & ~FlushECause;
// WFI terminates if any enabled interrupt is pending, even if global interrupts are disabled. It could also terminate with TW trap // WFI terminates if any enabled interrupt is pending, even if global interrupts are disabled. It could also terminate with TW trap
assign StallMCause = ((wfiM) & (~TrapM & ~IntPendingM)); assign StallMCause = ((wfiM) & (~TrapM & ~IntPendingM));
assign StallWCause = ((IFUStallF | LSUStallM) & ~TrapM); // | (FDivBusyE & ~TrapM & ~IntPendingM); assign StallWCause = (IFUStallF | LSUStallM) & ~TrapM;
assign #1 StallF = StallFCause | StallD; assign #1 StallF = StallFCause | StallD;
assign #1 StallD = StallDCause | StallE; assign #1 StallD = StallDCause | StallE;

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@ -390,7 +390,7 @@ module wallypipelinedcore (
.ReadDataW(ReadDataW[`FLEN-1:0]),// Read data from memory .ReadDataW(ReadDataW[`FLEN-1:0]),// Read data from memory
.ForwardedSrcAE, // Integer input being processed (from IEU) .ForwardedSrcAE, // Integer input being processed (from IEU)
.StallE, .StallM, .StallW, // stall signals from HZU .StallE, .StallM, .StallW, // stall signals from HZU
.TrapM, //.TrapM,
.FlushE, .FlushM, .FlushW, // flush signals from HZU .FlushE, .FlushM, .FlushW, // flush signals from HZU
.RdM, .RdW, // which FP register to write to (from IEU) .RdM, .RdW, // which FP register to write to (from IEU)
.STATUS_FS, // is floating-point enabled? .STATUS_FS, // is floating-point enabled?