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Cleaned up names in lsuvirtmem.

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This commit is contained in:
Ross Thompson 2022-02-21 16:44:30 -06:00
parent 3ba70b74d6
commit 414e73edd9
2 changed files with 8 additions and 6 deletions
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8
pipelined/src/lsu/lsuvirtmen.sv
View File

@ -75,13 +75,15 @@ module lsuvirtmem(
logic [2:0] HPTWSize; logic [2:0] HPTWSize;
logic SelReplayCPURequest; logic SelReplayCPURequest;
logic [11:0] PreLSUAdrE; logic [11:0] PreLSUAdrE;
logic ITLBMissOrDAFaultF; logic ITLBMissOrDAFaultF, ITLBMissOrDAFaultNoTrapF;
logic DTLBMissOrDAFaultM; logic DTLBMissOrDAFaultM, DTLBMissOrDAFaultNoTrapM;
logic HPTWWrite; logic HPTWWrite;
assign AnyCPUReqM = (|MemRWM) | (|AtomicM); assign AnyCPUReqM = (|MemRWM) | (|AtomicM);
assign ITLBMissOrDAFaultF = ITLBMissF | (`HPTW_WRITES_SUPPORTED & InstrDAPageFaultF); assign ITLBMissOrDAFaultF = ITLBMissF | (`HPTW_WRITES_SUPPORTED & InstrDAPageFaultF);
assign DTLBMissOrDAFaultM = DTLBMissM | (`HPTW_WRITES_SUPPORTED & DataDAPageFaultM); assign DTLBMissOrDAFaultM = DTLBMissM | (`HPTW_WRITES_SUPPORTED & DataDAPageFaultM);
assign ITLBMissOrDAFaultNoTrapF = ITLBMissOrDAFaultF & ~TrapM;
assign DTLBMissOrDAFaultNoTrapM = DTLBMissOrDAFaultM & ~TrapM;
interlockfsm interlockfsm ( interlockfsm interlockfsm (
.clk, .reset, .AnyCPUReqM, .ITLBMissOrDAFaultF, .ITLBWriteF, .clk, .reset, .AnyCPUReqM, .ITLBMissOrDAFaultF, .ITLBWriteF,
.DTLBMissOrDAFaultM, .DTLBWriteM, .TrapM, .DCacheStallM, .DTLBMissOrDAFaultM, .DTLBWriteM, .TrapM, .DCacheStallM,
@ -89,7 +91,7 @@ module lsuvirtmem(
hptw hptw( // *** remove logic from (), mention this in style guide CH3 hptw hptw( // *** remove logic from (), mention this in style guide CH3
.clk, .reset, .SATP_REGW, .PCF, .IEUAdrExtM, .MemRWM, .AtomicM, .clk, .reset, .SATP_REGW, .PCF, .IEUAdrExtM, .MemRWM, .AtomicM,
.STATUS_MXR, .STATUS_SUM, .STATUS_MPRV, .STATUS_MPP, .PrivilegeModeW, .STATUS_MXR, .STATUS_SUM, .STATUS_MPRV, .STATUS_MPP, .PrivilegeModeW,
.ITLBMissF(ITLBMissOrDAFaultF & ~TrapM), .DTLBMissM(DTLBMissOrDAFaultM & ~TrapM), // *** Fix me. *** I'm not sure ITLBMiss should be suppressed on TrapM. .ITLBMissOrDAFaultNoTrapF, .DTLBMissOrDAFaultNoTrapM,
.PTE, .PageType, .ITLBWriteF, .DTLBWriteM, .HPTWReadPTE(ReadDataM), .PTE, .PageType, .ITLBWriteF, .DTLBWriteM, .HPTWReadPTE(ReadDataM),
.DCacheStallM, .HPTWAdr, .HPTWRead, .HPTWWrite, .HPTWSize); .DCacheStallM, .HPTWAdr, .HPTWRead, .HPTWWrite, .HPTWSize);

6
pipelined/src/mmu/hptw.sv
View File

@ -41,7 +41,7 @@ module hptw
input logic STATUS_MXR, STATUS_SUM, STATUS_MPRV, input logic STATUS_MXR, STATUS_SUM, STATUS_MPRV,
input logic [1:0] STATUS_MPP, input logic [1:0] STATUS_MPP,
input logic [1:0] PrivilegeModeW, input logic [1:0] PrivilegeModeW,
(* mark_debug = "true" *) input logic ITLBMissF, DTLBMissM, // TLB Miss (* mark_debug = "true" *) input logic ITLBMissOrDAFaultNoTrapF, DTLBMissOrDAFaultNoTrapM, // TLB Miss
input logic [`XLEN-1:0] HPTWReadPTE, // page table entry from LSU input logic [`XLEN-1:0] HPTWReadPTE, // page table entry from LSU
input logic DCacheStallM, // stall from LSU input logic DCacheStallM, // stall from LSU
output logic [`XLEN-1:0] PTE, // page table entry to TLBs output logic [`XLEN-1:0] PTE, // page table entry to TLBs
@ -82,14 +82,14 @@ module hptw
// Extract bits from CSRs and inputs // Extract bits from CSRs and inputs
assign SvMode = SATP_REGW[`XLEN-1:`XLEN-`SVMODE_BITS]; assign SvMode = SATP_REGW[`XLEN-1:`XLEN-`SVMODE_BITS];
assign BasePageTablePPN = SATP_REGW[`PPN_BITS-1:0]; assign BasePageTablePPN = SATP_REGW[`PPN_BITS-1:0];
assign TLBMiss = (DTLBMissM | ITLBMissF); assign TLBMiss = (DTLBMissOrDAFaultNoTrapM | ITLBMissOrDAFaultNoTrapF);
// Determine which address to translate // Determine which address to translate
assign TranslationVAdr = DTLBWalk ? IEUAdrExtM[`XLEN-1:0] : PCF; assign TranslationVAdr = DTLBWalk ? IEUAdrExtM[`XLEN-1:0] : PCF;
assign CurrentPPN = PTE[`PPN_BITS+9:10]; assign CurrentPPN = PTE[`PPN_BITS+9:10];
// State flops // State flops
flopenr #(1) TLBMissMReg(clk, reset, StartWalk, DTLBMissM, DTLBWalk); // when walk begins, record whether it was for DTLB (or record 0 for ITLB) flopenr #(1) TLBMissMReg(clk, reset, StartWalk, DTLBMissOrDAFaultNoTrapM, DTLBWalk); // when walk begins, record whether it was for DTLB (or record 0 for ITLB)
assign PRegEn = HPTWRead & ~DCacheStallM; assign PRegEn = HPTWRead & ~DCacheStallM;
flopenr #(`XLEN) PTEReg(clk, reset, PRegEn | UpdatePTE, NextPTE, PTE); // Capture page table entry from data cache flopenr #(`XLEN) PTEReg(clk, reset, PRegEn | UpdatePTE, NextPTE, PTE); // Capture page table entry from data cache