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				@ -43,7 +43,7 @@ module hazard (
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					);
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  logic                                       StallFCause, StallDCause, StallECause, StallMCause, StallWCause;
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					  logic                                       StallFCause, StallDCause, StallECause, StallMCause, StallWCause;
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  logic                                       FirstUnstalledD, FirstUnstalledE, FirstUnstalledM, FirstUnstalledW;
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					  logic                                       LatestUnstalledD, LatestUnstalledE, LatestUnstalledM, LatestUnstalledW;
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  logic                                       FlushDCause, FlushECause, FlushMCause, FlushWCause;
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					  logic                                       FlushDCause, FlushECause, FlushMCause, FlushWCause;
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  // stalls and flushes
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					  // stalls and flushes
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@ -95,14 +95,14 @@ module hazard (
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  assign #1 StallW = StallWCause;
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					  assign #1 StallW = StallWCause;
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  // detect the first stage that is not stalled
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					  // detect the first stage that is not stalled
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  assign FirstUnstalledD = ~StallD & StallF;
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					  assign LatestUnstalledD = ~StallD & StallF;
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  assign FirstUnstalledE = ~StallE & StallD;
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					  assign LatestUnstalledE = ~StallE & StallD;
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  assign FirstUnstalledM = ~StallM & StallE;
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					  assign LatestUnstalledM = ~StallM & StallE;
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  assign FirstUnstalledW = ~StallW & StallM;
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					  assign LatestUnstalledW = ~StallW & StallM;
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  // Each stage flushes if the previous stage is the last one stalled (for cause) or the system has reason to flush
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					  // Each stage flushes if the previous stage is the last one stalled (for cause) or the system has reason to flush
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  assign #1 FlushD = FirstUnstalledD | FlushDCause; 
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					  assign #1 FlushD = LatestUnstalledD | FlushDCause; 
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  assign #1 FlushE = FirstUnstalledE | FlushECause;
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					  assign #1 FlushE = LatestUnstalledE | FlushECause;
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  assign #1 FlushM = FirstUnstalledM | FlushMCause;
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					  assign #1 FlushM = LatestUnstalledM | FlushMCause;
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  assign #1 FlushW = FirstUnstalledW | FlushWCause;
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					  assign #1 FlushW = LatestUnstalledW | FlushWCause;
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endmodule
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					endmodule
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