forked from Github_Repos/cvw
		
	Controller fix
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				@ -173,7 +173,7 @@ module controller(
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  // ALU Decoding
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  assign sltD = (Funct3D == 3'b010);
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  assign sltuD = (Funct3D == 3'b011);
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  assign subD = (Funct3D == 3'b000 & Funct7D[5] & OpD[5]);
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  assign subD = (Funct3D == 3'b000 & Funct7D[5] & OpD[5]);  // OpD[5] needed; ***explain why
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  assign sraD = (Funct3D == 3'b101 & Funct7D[5]);
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  assign SubArithD = ALUOpD & (subD | sraD | sltD | sltuD); // TRUE for R-type subtracts and sra, slt, sltu
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  assign ALUControlD = {W64D, SubArithD, ALUOpD};
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