Xavi/cvw
1
0
Fork 0
forked from Github_Repos/cvw
Code Issues Pull Requests Packages Projects Releases Wiki Activity

Fixed syntax error which modelsim did not detect in my changes for making uart work with qemu's simulation.

Browse Source
This commit is contained in:
Ross Thompson 2021-11-23 10:00:32 -06:00
parent f12e7e1b68
commit 3fc370654d
2 changed files with 3 additions and 4 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
wally-pipelined/config/buildroot/wally-config.vh
View File

@ -107,7 +107,7 @@
`define GPIO_LOOPBACK_TEST 0 `define GPIO_LOOPBACK_TEST 0
// Hardware configuration // Hardware configuration
`define UART_PRESCALE 1 `define UART_PRESCALE 0
// Interrupt configuration // Interrupt configuration
`define PLIC_NUM_SRC 53 `define PLIC_NUM_SRC 53

5
wally-pipelined/src/uncore/uartPC16550D.sv
View File

@ -133,7 +133,7 @@ module uartPC16550D(
if (~HRESETn) begin // Table 3 Reset Configuration if (~HRESETn) begin // Table 3 Reset Configuration
IER <= #1 4'b0; IER <= #1 4'b0;
FCR <= #1 8'b0; FCR <= #1 8'b0;
if (~QEMU) LCR <= #1 8'b11 else LCR <= #1 8'b0; if (`QEMU) LCR <= #1 8'b11; else LCR <= #1 8'b0;
MCR <= #1 5'b0; MCR <= #1 5'b0;
LSR <= #1 8'b01100000; LSR <= #1 8'b01100000;
MSR <= #1 4'b0; MSR <= #1 4'b0;
@ -261,7 +261,6 @@ module uartPC16550D(
assign rxcentered = rxbaudpulse & (rxoversampledcnt == 4'b1000); // implies rxstate = UART_ACTIVE assign rxcentered = rxbaudpulse & (rxoversampledcnt == 4'b1000); // implies rxstate = UART_ACTIVE
endgenerate endgenerate
assign rxcentered = rxbaudpulse & (rxoversampledcnt == 2'b10); // implies rxstate = UART_ACTIVE
assign rxbitsexpected = 4'd1 + (4'd5 + {2'b00, LCR[1:0]}) + {3'b000, LCR[3]} + 4'd1; // start bit + data bits + (parity bit) + stop bit assign rxbitsexpected = 4'd1 + (4'd5 + {2'b00, LCR[1:0]}) + {3'b000, LCR[3]} + 4'd1; // start bit + data bits + (parity bit) + stop bit
/////////////////////////////////////////// ///////////////////////////////////////////
@ -382,7 +381,7 @@ module uartPC16550D(
assign txbitsexpected = 4'd1 + (4'd5 + {2'b00, LCR[1:0]}) + {3'b000, LCR[3]} + 4'd1 + {3'b000, LCR[2]} - 4'd1; // start bit + data bits + (parity bit) + stop bit(s) assign txbitsexpected = 4'd1 + (4'd5 + {2'b00, LCR[1:0]}) + {3'b000, LCR[3]} + 4'd1 + {3'b000, LCR[2]} - 4'd1; // start bit + data bits + (parity bit) + stop bit(s)
generate generate
if `QEMU if (`QEMU)
assign txnextbit = txbaudpulse & (txoversampledcnt == 2'b00); // implies txstate = UART_ACTIVE assign txnextbit = txbaudpulse & (txoversampledcnt == 2'b00); // implies txstate = UART_ACTIVE
else else
assign txnextbit = txbaudpulse & (txoversampledcnt == 4'b0000); // implies txstate = UART_ACTIVE assign txnextbit = txbaudpulse & (txoversampledcnt == 4'b0000); // implies txstate = UART_ACTIVE