forked from Github_Repos/cvw
Updated vcu118 constraints to run cpu at 38.43Mhz.
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parent
4b5ec21ef4
commit
3de5144ae4
@ -38,7 +38,7 @@ set_property -dict [list CONFIG.C0.ControllerType {DDR4_SDRAM} \
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CONFIG.C0.DDR4_AxiNarrowBurst {false} \
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CONFIG.C0.DDR4_AxiNarrowBurst {false} \
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CONFIG.Reference_Clock {Differential} \
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CONFIG.Reference_Clock {Differential} \
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CONFIG.ADDN_UI_CLKOUT1.INSERT_VIP {0} \
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CONFIG.ADDN_UI_CLKOUT1.INSERT_VIP {0} \
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CONFIG.ADDN_UI_CLKOUT1_FREQ_HZ {35} \
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CONFIG.ADDN_UI_CLKOUT1_FREQ_HZ {38} \
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CONFIG.ADDN_UI_CLKOUT2.INSERT_VIP {0} \
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CONFIG.ADDN_UI_CLKOUT2.INSERT_VIP {0} \
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CONFIG.ADDN_UI_CLKOUT2_FREQ_HZ {300} \
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CONFIG.ADDN_UI_CLKOUT2_FREQ_HZ {300} \
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CONFIG.ADDN_UI_CLKOUT3.INSERT_VIP {0} \
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CONFIG.ADDN_UI_CLKOUT3.INSERT_VIP {0} \
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@ -21,8 +21,8 @@
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cpus {
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cpus {
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#address-cells = <0x01>;
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#address-cells = <0x01>;
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#size-cells = <0x00>;
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#size-cells = <0x00>;
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clock-frequency = <0x211D0D0>;
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clock-frequency = <0x24AE230>;
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timebase-frequency = <0x211D0D0>;
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timebase-frequency = <0x24AE230>;
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cpu@0 {
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cpu@0 {
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phandle = <0x01>;
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phandle = <0x01>;
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@ -51,7 +51,7 @@
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uart@10000000 {
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uart@10000000 {
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interrupts = <0x0a>;
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interrupts = <0x0a>;
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interrupt-parent = <0x03>;
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interrupt-parent = <0x03>;
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clock-frequency = <0x211D0D0>;
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clock-frequency = <0x24AE230>;
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reg = <0x00 0x10000000 0x00 0x100>;
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reg = <0x00 0x10000000 0x00 0x100>;
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compatible = "ns16550a";
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compatible = "ns16550a";
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};
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};
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