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Simplified intdiv selection logic to muxes

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David Harris 2023-01-01 14:04:37 -08:00
parent f8af51e07b
commit 3d5acc7c2a
1 changed files with 14 additions and 20 deletions
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34
pipelined/src/fpu/fdivsqrt/fdivsqrtpostproc.sv
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@ -52,8 +52,7 @@ module fdivsqrtpostproc(
logic [`DIVb:0] PreQmM; logic [`DIVb:0] PreQmM;
logic NegStickyM; logic NegStickyM;
logic weq0E, weq0M, WZeroM; logic weq0E, weq0M, WZeroM;
logic signed [`DIVb+3:0] PreResultM, PreFPIntDivResultM; logic [`XLEN-1:0] IntDivResultM;
logic [`XLEN-1:0] SpecialFPIntDivResultM;
////////////////////////// //////////////////////////
// Execute Stage: Detect early termination for an exact result // Execute Stage: Detect early termination for an exact result
@ -99,9 +98,11 @@ module fdivsqrtpostproc(
mux2 #(`DIVb+1) preqmmux(FirstU, FirstUM, NegStickyM, PreQmM); // Select U or U-1 depending on negative sticky bit mux2 #(`DIVb+1) preqmmux(FirstU, FirstUM, NegStickyM, PreQmM); // Select U or U-1 depending on negative sticky bit
mux2 #(`DIVb+1) qmmux(PreQmM, (PreQmM << 1), SqrtM, QmM); mux2 #(`DIVb+1) qmmux(PreQmM, (PreQmM << 1), SqrtM, QmM);
// Integer quotient or remainder correctoin, normalization, and special cases
if (`IDIV_ON_FPU) begin:intpostproc // Int supported if (`IDIV_ON_FPU) begin:intpostproc // Int supported
logic [`DIVBLEN:0] NormShiftM; logic [`DIVBLEN:0] NormShiftM;
logic [`DIVb+3:0] UnsignedQuotM, NormRemM, NormRemDM, NormQuotM; logic [`DIVb+3:0] UnsignedQuotM, NormRemM, NormRemDM, NormQuotM;
logic signed [`DIVb+3:0] PreResultM, PreIntResultM;
assign W = $signed(Sum) >>> `LOGR; assign W = $signed(Sum) >>> `LOGR;
assign DM = {4'b0001, D}; assign DM = {4'b0001, D};
@ -113,34 +114,27 @@ module fdivsqrtpostproc(
mux2 #(`DIVb+4) quotresmux(UnsignedQuotM, -UnsignedQuotM, NegQuotM, NormQuotM); mux2 #(`DIVb+4) quotresmux(UnsignedQuotM, -UnsignedQuotM, NegQuotM, NormQuotM);
// Select quotient or remainder and do normalization shift // Select quotient or remainder and do normalization shift
always_comb begin mux2 #(`DIVBLEN+1) normshiftmux(((`DIVBLEN+1)'(`DIVb) - (nM * (`DIVBLEN+1)'(`LOGR))), (mM + (`DIVBLEN+1)'(`DIVa)), RemOpM, NormShiftM);
if (RemOpM) begin mux2 #(`DIVb+4) presresultmux(NormQuotM, NormRemM, RemOpM, PreResultM);
NormShiftM = ALTBM ? 0 : (mM + (`DIVBLEN+1)'(`DIVa)); // no postshift if forwarding input A to remainder assign PreIntResultM = $signed(PreResultM >>> NormShiftM);
PreResultM = NormRemM;
end else begin
NormShiftM = ((`DIVBLEN+1)'(`DIVb) - (nM * (`DIVBLEN+1)'(`LOGR)));
PreResultM = NormQuotM;
end
PreFPIntDivResultM = $signed(PreResultM >>> NormShiftM); // *** rename to PreIntResultM?
end
// special case logic // special case logic
// terminates immediately when B is Zero (div 0) or |A| has more leading 0s than |B| // terminates immediately when B is Zero (div 0) or |A| has more leading 0s than |B|
always_comb always_comb
if (BZeroM) begin // Divide by zero if (BZeroM) begin // Divide by zero
if (RemOpM) SpecialFPIntDivResultM = AM; // *** rename to IntDivResult? if (RemOpM) IntDivResultM = AM;
else SpecialFPIntDivResultM = {(`XLEN){1'b1}}; else IntDivResultM = {(`XLEN){1'b1}};
end else if (ALTBM) begin // Numerator is zero end else if (ALTBM) begin // Numerator is zero
if (RemOpM) SpecialFPIntDivResultM = AM; if (RemOpM) IntDivResultM = AM;
else SpecialFPIntDivResultM = '0; else IntDivResultM = '0;
end else SpecialFPIntDivResultM = PreFPIntDivResultM[`XLEN-1:0]; end else IntDivResultM = PreIntResultM[`XLEN-1:0];
// sign extend result for W64 // sign extend result for W64
if (`XLEN==64) begin if (`XLEN==64) begin
mux2 #(64) resmux(SpecialFPIntDivResultM[`XLEN-1:0], mux2 #(64) resmux(IntDivResultM[`XLEN-1:0],
{{(`XLEN-32){SpecialFPIntDivResultM[31]}}, SpecialFPIntDivResultM[31:0]}, // Sign extending in case of W64 {{(`XLEN-32){IntDivResultM[31]}}, IntDivResultM[31:0]}, // Sign extending in case of W64
W64M, FPIntDivResultM); W64M, FPIntDivResultM);
end else end else
assign FPIntDivResultM = SpecialFPIntDivResultM[`XLEN-1:0]; assign FPIntDivResultM = IntDivResultM[`XLEN-1:0];
end end
endmodule endmodule