Xavi/cvw
1
0
Fork 0
forked from Github_Repos/cvw
Code Issues Pull Requests Packages Projects Releases Wiki Activity

Completely stripped down imperas simulation.

Browse Source 
run with
vsim -c -do "do wally-pipelined-imperas.do rv64gc"
This commit is contained in:
Ross Thompson 2023-01-12 12:48:38 -06:00
parent 2f2f3d6da5
commit 3cc37e3f12
2 changed files with 1 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
pipelined/regression/wally-pipelined-imperas.do
View File

@ -33,7 +33,7 @@ vlib work
# remove +acc flag for faster sim during regressions if there is no need to access internal signals # remove +acc flag for faster sim during regressions if there is no need to access internal signals
# *** modelsim won't take `PA_BITS, but will take other defines for the lengths of DTIM_RANGE and IROM_LEN. For now just live with the warnings. # *** modelsim won't take `PA_BITS, but will take other defines for the lengths of DTIM_RANGE and IROM_LEN. For now just live with the warnings.
vlog +incdir+../config/$1 +incdir+../config/shared ../testbench/testbench_imperas.sv ../testbench/common/*.sv ../src/*/*.sv ../src/*/*/*.sv -suppress 2583 -suppress 7063 vlog +incdir+../config/$1 +incdir+../config/shared ../testbench/testbench_imperas.sv ../testbench/common/*.sv ../src/*/*.sv ../src/*/*/*.sv -suppress 2583 -suppress 7063
vopt +acc work.testbench -G TEST=$2 -G DEBUG=1 -o workopt vopt +acc work.testbench -G DEBUG=1 -o workopt
vsim workopt +nowarn3829 -fatal 7 vsim workopt +nowarn3829 -fatal 7
view wave view wave
#-- display input and output signals as hexidecimal values #-- display input and output signals as hexidecimal values

1
pipelined/testbench/testbench_imperas.sv
View File

@ -34,7 +34,6 @@
module testbench; module testbench;
parameter DEBUG=0; parameter DEBUG=0;
parameter TEST="none";
logic clk; logic clk;
logic reset_ext, reset; logic reset_ext, reset;