forked from Github_Repos/cvw
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
This commit is contained in:
commit
3ba70b74d6
@ -3,5 +3,5 @@ all: sqrttestgen testgen
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|||||||
sqrttestgen: sqrttestgen.c
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sqrttestgen: sqrttestgen.c
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gcc sqrttestgen.c -lm -o sqrttestgen
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gcc sqrttestgen.c -lm -o sqrttestgen
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|
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testgen: testgen.c
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testgen: exptestgen.c
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gcc testgen.c -lm -o testgen
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gcc exptestgen.c -lm -o exptestgen
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|
BIN
pipelined/srt/exptestgen
Executable file
BIN
pipelined/srt/exptestgen
Executable file
Binary file not shown.
121
pipelined/srt/exptestgen.c
Normal file
121
pipelined/srt/exptestgen.c
Normal file
@ -0,0 +1,121 @@
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/* testgen.c */
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/* Written 2/19/2022 by David Harris
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This program creates test vectors for mantissa and exponent components
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of an IEEE floating point divider.
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Builds upon program that creates test vectors for mantissa component only.
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*/
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/* #includes */
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#include <stdio.h>
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#include <stdlib.h>
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#include <math.h>
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/* Constants */
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#define ENTRIES 17
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#define RANDOM_VECS 500
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// #define BIAS 1023 // Bias is for double precision
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/* Prototypes */
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void output(FILE *fptr, int e1, double a, int e2, double b, int r_exp, double r_mantissa);
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void printhex(FILE *fptr, double x);
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double random_input(void);
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double random_input_e(void);
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/* Main */
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void main(void)
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{
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FILE *fptr;
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// e1 & e2 are exponents
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// a & b are mantissas
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// r_mantissa is result of mantissa divsion
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// r_exp is result of exponent division
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double a, b, r_mantissa, r_exp;
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int e1, e2;
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double mantissa[ENTRIES] = {1, 1.5, 1.25, 1.125, 1.0625,
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1.75, 1.875, 1.99999,
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1.1, 1.2, 1.01, 1.001, 1.0001,
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1/1.1, 1/1.5, 1/1.25, 1/1.125};
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int exponent[ENTRIES] = {1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17};
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int i, j;
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int bias = 1023;
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if ((fptr = fopen("testvectors","w")) == NULL) {
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fprintf(stderr, "Couldn't write testvectors file\n");
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exit(1);
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}
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for (i=0; i<ENTRIES; i++) {
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b = mantissa[i];
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e2 = exponent[i] + bias;
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for (j=0; j<ENTRIES; j++) {
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a = mantissa[j];
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e1 = exponent[j] + bias;
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r_mantissa = a/b;
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r_exp = e1 - e2 + bias;
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output(fptr, e1, a, e2, b, r_exp, r_mantissa);
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|
}
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|
}
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|
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|
// for (i = 0; i< RANDOM_VECS; i++) {
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// a = random_input();
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// b = random_input();
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// e1 = random_input_e() + BIAS; // make new random input function for exponents
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// e2 = random_input_e() + BIAS;
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// r_mantissa = a/b;
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// r_exp = e1 - e2 + BIAS;
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// output(fptr, e1, a, e2, b, r_exp, r_mantissa);
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// }
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fclose(fptr);
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|
}
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/* Functions */
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|
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void output(FILE *fptr, int e1, double a, int e2, double b, int r_exp, double r_mantissa)
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|
{
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fprintf(fptr, "%03x", e1);
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//printhex(fptr, e1, exp);
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printhex(fptr, a);
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fprintf(fptr, "_");
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fprintf(fptr, "%03x", e2);
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//printhex(fptr, e2, exp);
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printhex(fptr, b);
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fprintf(fptr, "_");
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fprintf(fptr, "%03x", r_exp);
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//printhex(fptr, r_exp, exp);
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printhex(fptr, r_mantissa);
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fprintf(fptr, "\n");
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|
}
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|
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void printhex(FILE *fptr, double m)
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|
{
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|
int i, val, len;
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|
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|
len = 52;
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while (m<1) m *= 2;
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while (m>2) m /= 2;
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for (i=0; i<len; i+=4) {
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|
m = m - floor(m);
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|
m = m * 16;
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|
val = (int)(m)%16;
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fprintf(fptr, "%x", val);
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|
}
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|
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|
}
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double random_input(void)
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|
{
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|
return 1.0 + rand()/32767.0;
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|
}
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|
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double random_input_e(void)
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|
{
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return rand() % 300 + 1;
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|
}
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|
@ -1 +1,2 @@
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verilator --lint-only --top-module srt srt.sv -I../config/rv64gc -I../config/shared ../src/generic/*.sv ../src/generic/flop/*.sv
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verilator --lint-only --top-module srt srt.sv -I../config/rv64gc -I../config/shared ../src/generic/*.sv ../src/generic/flop/*.sv
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||||||
|
verilator --lint-only --top-module testbench testbench.sv -I../config/rv64gc -I../config/shared ../src/generic/*.sv ../src/generic/flop/*.sv ../src/fpu/unpacking.sv
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@ -37,6 +37,8 @@ module srt #(parameter Nf=52) (
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input logic Flush, // *** multiple pipe stages
|
input logic Flush, // *** multiple pipe stages
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// Floating Point Inputs
|
// Floating Point Inputs
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||||||
// later add exponents, signs, special cases
|
// later add exponents, signs, special cases
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|
input logic [10:0] SrcXExpE, SrcYExpE, // exponents, for double precision exponents are 11 bits
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|
// end of floating point inputs
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input logic [Nf-1:0] SrcXFrac, SrcYFrac,
|
input logic [Nf-1:0] SrcXFrac, SrcYFrac,
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input logic [`XLEN-1:0] SrcA, SrcB,
|
input logic [`XLEN-1:0] SrcA, SrcB,
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||||||
input logic [1:0] Fmt, // Floats: 00 = 16 bit, 01 = 32 bit, 10 = 64 bit, 11 = 128 bit
|
input logic [1:0] Fmt, // Floats: 00 = 16 bit, 01 = 32 bit, 10 = 64 bit, 11 = 128 bit
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||||||
@ -45,6 +47,7 @@ module srt #(parameter Nf=52) (
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input logic Int, // Choose integer inputss
|
input logic Int, // Choose integer inputss
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input logic Sqrt, // perform square root, not divide
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input logic Sqrt, // perform square root, not divide
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output logic [Nf-1:0] Quot, Rem, // *** later handle integers
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output logic [Nf-1:0] Quot, Rem, // *** later handle integers
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output logic [10:0] Exp, // output exponent is hardcoded for 11 bits for double precision
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output logic [3:0] Flags
|
output logic [3:0] Flags
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);
|
);
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@ -78,6 +81,9 @@ module srt #(parameter Nf=52) (
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// Partial Product Generation
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// Partial Product Generation
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csa csa(WS, WC, Dsel, qp, WSA, WCA);
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csa csa(WS, WC, Dsel, qp, WSA, WCA);
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// Exponent division
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exp exp(SrcXExpE, SrcYExpE, Exp);
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srtpostproc postproc(rp, rm, Quot);
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srtpostproc postproc(rp, rm, Quot);
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endmodule
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endmodule
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|
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@ -247,6 +253,14 @@ module csa #(parameter N=56) (
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(in2[54:0] & in3[54:0]), cin};
|
(in2[54:0] & in3[54:0]), cin};
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endmodule
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endmodule
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||||||
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//////////////
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// exponent //
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//////////////
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module exp(input [10:0] e1, e2,
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output [10:0] e); // for double precision, exponent is 11 bits
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|
assign e = (e1 - e2) + 11'd1023; // bias is hardcoded
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|
endmodule
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|
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||||||
//////////////
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//////////////
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// finaladd //
|
// finaladd //
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||||||
//////////////
|
//////////////
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|
@ -14,49 +14,6 @@
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|
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||||||
`include "wally-config.vh"
|
`include "wally-config.vh"
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|
|
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// will also be used for integer division so keep in mind when naming modules/signals
|
|
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|
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/////////////////
|
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// srt_divide //
|
|
||||||
////////////////
|
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module srt_divide(input logic clk,
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|
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input logic req,
|
|
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input logic sqrt, // 1 to compute sqrt(a), 0 to compute a/b
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|
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input logic [63:0] a, b, // input numbers
|
|
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output logic [54:0] rp, rm,
|
|
||||||
output logic [10:0] expE);
|
|
||||||
|
|
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// output logic from Unpackers
|
|
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logic XSgnE, YSgnE, ZSgnE;
|
|
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logic [10:0] XExpE, YExpE, ZExpE; // exponent
|
|
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logic [52:0] XManE, YManE, ZManE;
|
|
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logic XNormE;
|
|
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logic XNaNE, YNaNE, ZNaNE;
|
|
||||||
logic XSNaNE, YSNaNE, ZSNaNE;
|
|
||||||
logic XDenormE, YDenormE, ZDenormE; // denormals
|
|
||||||
logic XZeroE, YZeroE, ZZeroE;
|
|
||||||
logic [10:0] BiasE; // currrently hardcoded, will probs be removed
|
|
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logic XInfE, YInfE, ZInfE;
|
|
||||||
logic XExpMaxE; // says exponent is all ones, can ignore
|
|
||||||
|
|
||||||
// have Unpackers
|
|
||||||
// have mantissa divider
|
|
||||||
// exponent divider
|
|
||||||
|
|
||||||
// hopefully having the .* here works for unpacker --- nope it doesn't
|
|
||||||
unpack unpacking(a, b, 0, 1'b1, 0, XSgnE, YSgnE, ZSgnE, XExpE, YExpE, ZExpE, XManE, YManE, ZManE, XNormE,XNaNE, YNaNE, ZNaNE,XSNaNE, YSNaNE, ZSNaNE,XDenormE, YDenormE, ZDenormE,XZeroE, YZeroE, ZZeroE,BiasE,XInfE, YInfE, ZInfE,XExpMaxE);
|
|
||||||
srt srt(clk, req, XManE[51:0], YManE[51:0], rp, rm);
|
|
||||||
exp exp(XexpE, YExpE, expE);
|
|
||||||
endmodule
|
|
||||||
|
|
||||||
// exponent module
|
|
||||||
// first iteration
|
|
||||||
module exp(input [10:0] e1, e2,
|
|
||||||
output [10:0] e); // for a 64 bit number, exponent section is 11 bits
|
|
||||||
assign e = (e1 - e2) + 11'd1023; // bias is hardcoded
|
|
||||||
endmodule
|
|
||||||
|
|
||||||
|
|
||||||
/////////
|
/////////
|
||||||
// srt //
|
// srt //
|
||||||
/////////
|
/////////
|
||||||
@ -84,12 +41,12 @@ module srt(input logic clk,
|
|||||||
// When start is asserted, the inputs are loaded into the divider.
|
// When start is asserted, the inputs are loaded into the divider.
|
||||||
// Otherwise, the divisor is retained and the partial remainder
|
// Otherwise, the divisor is retained and the partial remainder
|
||||||
// is fed back for the next iteration.
|
// is fed back for the next iteration.
|
||||||
mux2_special psmux({psa[54:0], 1'b0}, {4'b0001, a}, req, psn);
|
mux2 psmux({psa[54:0], 1'b0}, {4'b0001, a}, req, psn);
|
||||||
flop_special psflop(clk, psn, ps);
|
flop psflop(clk, psn, ps);
|
||||||
mux2_special pcmux({pca[54:0], 1'b0}, 56'b0, req, pcn);
|
mux2 pcmux({pca[54:0], 1'b0}, 56'b0, req, pcn);
|
||||||
flop_special pcflop(clk, pcn, pc);
|
flop pcflop(clk, pcn, pc);
|
||||||
mux2_special dmux(d, {4'b0001, b}, req, dn);
|
mux2 dmux(d, {4'b0001, b}, req, dn);
|
||||||
flop_special dflop(clk, dn, d);
|
flop dflop(clk, dn, d);
|
||||||
|
|
||||||
// Quotient Selection logic
|
// Quotient Selection logic
|
||||||
// Given partial remainder, select quotient of +1, 0, or -1 (qp, qz, pm)
|
// Given partial remainder, select quotient of +1, 0, or -1 (qp, qz, pm)
|
||||||
@ -99,7 +56,7 @@ module srt(input logic clk,
|
|||||||
|
|
||||||
// Divisor Selection logic
|
// Divisor Selection logic
|
||||||
inv dinv(d, d_b);
|
inv dinv(d, d_b);
|
||||||
mux3_special divisorsel(d_b, 56'b0, d, qp, qz, qm, dsel);
|
mux3 divisorsel(d_b, 56'b0, d, qp, qz, qm, dsel);
|
||||||
|
|
||||||
// Partial Product Generation
|
// Partial Product Generation
|
||||||
csa csa(ps, pc, dsel, qp, psa, pca);
|
csa csa(ps, pc, dsel, qp, psa, pca);
|
||||||
@ -108,7 +65,7 @@ endmodule
|
|||||||
//////////
|
//////////
|
||||||
// mux2 //
|
// mux2 //
|
||||||
//////////
|
//////////
|
||||||
module mux2_special(input logic [55:0] in0, in1,
|
module mux2(input logic [55:0] in0, in1,
|
||||||
input logic sel,
|
input logic sel,
|
||||||
output logic [55:0] out);
|
output logic [55:0] out);
|
||||||
|
|
||||||
@ -118,7 +75,7 @@ endmodule
|
|||||||
//////////
|
//////////
|
||||||
// flop //
|
// flop //
|
||||||
//////////
|
//////////
|
||||||
module flop_special(clk, in, out);
|
module flop(clk, in, out);
|
||||||
input clk;
|
input clk;
|
||||||
input [55:0] in;
|
input [55:0] in;
|
||||||
output [55:0] out;
|
output [55:0] out;
|
||||||
@ -204,9 +161,9 @@ module inv(input logic [55:0] in,
|
|||||||
endmodule
|
endmodule
|
||||||
|
|
||||||
//////////
|
//////////
|
||||||
// mux3_special //
|
// mux3 //
|
||||||
//////////
|
//////////
|
||||||
module mux3_special(in0, in1, in2, sel0, sel1, sel2, out);
|
module mux3(in0, in1, in2, sel0, sel1, sel2, out);
|
||||||
input [55:0] in0;
|
input [55:0] in0;
|
||||||
input [55:0] in1;
|
input [55:0] in1;
|
||||||
input [55:0] in2;
|
input [55:0] in2;
|
||||||
@ -317,24 +274,6 @@ module testbench;
|
|||||||
logic [51:0] r;
|
logic [51:0] r;
|
||||||
logic [54:0] rp, rm; // positive quotient digits
|
logic [54:0] rp, rm; // positive quotient digits
|
||||||
|
|
||||||
//input logic [63:0] X, Y, Z, - numbers
|
|
||||||
//input logic FmtE, ---- format, 1 is for double precision, 0 is single
|
|
||||||
//input logic [2:0] FOpCtrlE, ---- controling operations for FPU, 1 is sqrt, 0 is divide
|
|
||||||
// all variables are commented in fpu.sv
|
|
||||||
|
|
||||||
// output logic from Unpackers
|
|
||||||
logic XSgnE, YSgnE, ZSgnE;
|
|
||||||
logic [10:0] XExpE, YExpE, ZExpE; // exponent
|
|
||||||
logic [52:0] XManE, YManE, ZManE;
|
|
||||||
logic XNormE;
|
|
||||||
logic XNaNE, YNaNE, ZNaNE;
|
|
||||||
logic XSNaNE, YSNaNE, ZSNaNE;
|
|
||||||
logic XDenormE, YDenormE, ZDenormE; // denormals
|
|
||||||
logic XZeroE, YZeroE, ZZeroE;
|
|
||||||
logic [10:0] BiasE; // currrently hardcoded, will probs be removed
|
|
||||||
logic XInfE, YInfE, ZInfE;
|
|
||||||
logic XExpMaxE; // says exponent is all ones, can ignore
|
|
||||||
|
|
||||||
// Test parameters
|
// Test parameters
|
||||||
parameter MEM_SIZE = 40000;
|
parameter MEM_SIZE = 40000;
|
||||||
parameter MEM_WIDTH = 52+52+52;
|
parameter MEM_WIDTH = 52+52+52;
|
||||||
@ -350,15 +289,8 @@ module testbench;
|
|||||||
logic [51:0] correctr, nextr;
|
logic [51:0] correctr, nextr;
|
||||||
integer testnum, errors;
|
integer testnum, errors;
|
||||||
|
|
||||||
// Unpackers
|
|
||||||
unpacking unpack(.X({12'b100010000010,a}), .Y({12'b100010000001,b}), .Z(0), .FmtE(1'b1), .FOpCtrlE(0), .*);
|
|
||||||
|
|
||||||
// Divider
|
// Divider
|
||||||
srt srt(.clk(clk), .req(req), .sqrt(1'b0), .a(XManE[51:0]), .b(YManE[51:0]), .rp(rp),.rm(rm));
|
srt srt(clk, req, a, b, rp, rm);
|
||||||
|
|
||||||
//srt srt(.clk(clk), .req(req), .sqrt(1'b0), .a(a), .b(b), .rp(rp),.rm(rm));
|
|
||||||
|
|
||||||
// Divider + unpacker
|
|
||||||
|
|
||||||
// Final adder converts quotient digits to 2's complement & normalizes
|
// Final adder converts quotient digits to 2's complement & normalizes
|
||||||
finaladd finaladd(rp, rm, r);
|
finaladd finaladd(rp, rm, r);
|
||||||
|
@ -40,33 +40,66 @@ module testbench;
|
|||||||
logic clk;
|
logic clk;
|
||||||
logic req;
|
logic req;
|
||||||
logic done;
|
logic done;
|
||||||
logic [51:0] a;
|
logic [63:0] a;
|
||||||
logic [51:0] b;
|
logic [63:0] b;
|
||||||
|
logic [63:0] result;
|
||||||
logic [51:0] r;
|
logic [51:0] r;
|
||||||
logic [54:0] rp, rm; // positive quotient digits
|
logic [54:0] rp, rm; // positive quotient digits
|
||||||
|
logic [10:0] e; // output exponent
|
||||||
|
|
||||||
|
// input logic for Unpacker
|
||||||
|
// input logic [63:0] X, Y, Z, - numbers
|
||||||
|
// input logic FmtE, ---- format, 1 is for double precision, 0 is single
|
||||||
|
// input logic [2:0] FOpCtrlE, ---- controling operations for FPU, 1 is sqrt, 0 is divide
|
||||||
|
// all variables are commented in fpu.sv
|
||||||
|
|
||||||
|
// output logic from Unpacker
|
||||||
|
logic XSgnE, YSgnE, ZSgnE;
|
||||||
|
logic [10:0] XExpE, YExpE, ZExpE; // exponent
|
||||||
|
logic [52:0] XManE, YManE, ZManE;
|
||||||
|
logic XNormE;
|
||||||
|
logic XNaNE, YNaNE, ZNaNE;
|
||||||
|
logic XSNaNE, YSNaNE, ZSNaNE;
|
||||||
|
logic XDenormE, YDenormE, ZDenormE; // denormals
|
||||||
|
logic XZeroE, YZeroE, ZZeroE;
|
||||||
|
logic [10:0] BiasE; // currrently hardcoded, will probs be removed
|
||||||
|
logic XInfE, YInfE, ZInfE;
|
||||||
|
logic XExpMaxE; // says exponent is all ones, can ignore
|
||||||
|
|
||||||
// Test parameters
|
// Test parameters
|
||||||
parameter MEM_SIZE = 40000;
|
parameter MEM_SIZE = 60000;
|
||||||
parameter MEM_WIDTH = 52+52+52;
|
parameter MEM_WIDTH = 64+64+64;
|
||||||
|
|
||||||
`define memr 51:0
|
`define memr 63:0
|
||||||
`define memb 103:52
|
`define memb 127:64
|
||||||
`define mema 155:104
|
`define mema 191:128
|
||||||
|
|
||||||
// Test logicisters
|
// Test logicisters
|
||||||
logic [MEM_WIDTH-1:0] Tests [0:MEM_SIZE]; // Space for input file
|
logic [MEM_WIDTH-1:0] Tests [0:MEM_SIZE]; // Space for input file
|
||||||
logic [MEM_WIDTH-1:0] Vec; // Verilog doesn't allow direct access to a
|
logic [MEM_WIDTH-1:0] Vec; // Verilog doesn't allow direct access to a
|
||||||
// bit field of an array
|
// bit field of an array
|
||||||
logic [51:0] correctr, nextr, diffn, diffp;
|
logic [63:0] correctr, nextr, diffn, diffp;
|
||||||
integer testnum, errors;
|
integer testnum, errors;
|
||||||
|
|
||||||
|
// Unpacker
|
||||||
|
// Note: BiasE will probably get taken out eventually
|
||||||
|
unpacking unpack(.X({1'b1,a[62:0]}), .Y({1'b1,b[62:0]}), .Z(64'b0), .FmtE(1'b1), .FOpCtrlE(3'b0),
|
||||||
|
.XSgnE(XSgnE), .YSgnE(YSgnE), .ZSgnE(ZSgnE), .XExpE(XExpE), .YExpE(YExpE), .ZExpE(ZExpE),
|
||||||
|
.XManE(XManE), .YManE(YManE), .ZManE(ZManE), .XNormE(XNormE), .XNaNE(XNaNE), .YNaNE(YNaNE), .ZNaNE(ZNaNE),
|
||||||
|
.XSNaNE(XSNaNE), .YSNaNE(YSNaNE), .ZSNaNE(ZSNaNE), .XDenormE(XDenormE), .YDenormE(YDenormE), .ZDenormE(ZDenormE),
|
||||||
|
.XZeroE(XZeroE), .YZeroE(YZeroE), .ZZeroE(ZZeroE), .BiasE(BiasE),
|
||||||
|
.XInfE(XInfE), .YInfE(YInfE), .ZInfE(ZInfE), .XExpMaxE(XExpMaxE));
|
||||||
|
|
||||||
// Divider
|
// Divider
|
||||||
srt #(52) srt(.clk, .Start(req),
|
srt #(52) srt(.clk, .Start(req),
|
||||||
.Stall(1'b0), .Flush(1'b0),
|
.Stall(1'b0), .Flush(1'b0),
|
||||||
.SrcXFrac(a), .SrcYFrac(b),
|
.SrcXExpE(XExpE), .SrcYExpE(YExpE),
|
||||||
|
.SrcXFrac(XManE[51:0]), .SrcYFrac(YManE[51:0]),
|
||||||
.SrcA('0), .SrcB('0), .Fmt(2'b00),
|
.SrcA('0), .SrcB('0), .Fmt(2'b00),
|
||||||
.W64(1'b0), .Signed(1'b0), .Int(1'b0), .Sqrt(1'b0),
|
.W64(1'b0), .Signed(1'b0), .Int(1'b0), .Sqrt(1'b0),
|
||||||
.Quot(r), .Rem(), .Flags());
|
.Quot(r), .Rem(), .Exp(e), .Flags());
|
||||||
|
|
||||||
|
assign result = {1'b0, e, r};
|
||||||
|
|
||||||
// Counter
|
// Counter
|
||||||
counter counter(clk, req, done);
|
counter counter(clk, req, done);
|
||||||
@ -100,16 +133,18 @@ module testbench;
|
|||||||
if (done)
|
if (done)
|
||||||
begin
|
begin
|
||||||
req <= #5 1;
|
req <= #5 1;
|
||||||
diffp = correctr - r;
|
diffp = correctr - result;
|
||||||
diffn = r - correctr;
|
diffn = result - correctr;
|
||||||
if (($signed(diffn) > 1) | ($signed(diffp) > 1)) // check if accurate to 1 ulp
|
if (($signed(diffn) > 1) | ($signed(diffp) > 1)) // check if accurate to 1 ulp
|
||||||
begin
|
begin
|
||||||
errors = errors+1;
|
errors = errors+1;
|
||||||
$display("result was %h, should be %h %h %h\n", r, correctr, diffn, diffp);
|
$display("a = %h b = %h result = %h",a,b,correctr);
|
||||||
|
$display("result was %h, should be %h %h %h\n", result, correctr, diffn, diffp);
|
||||||
|
$display("at fail");
|
||||||
$display("failed\n");
|
$display("failed\n");
|
||||||
$stop;
|
$stop;
|
||||||
end
|
end
|
||||||
if (a === 52'hxxxxxxxxxxxxx)
|
if (a === 64'hxxxxxxxxxxxxxxxx)
|
||||||
begin
|
begin
|
||||||
$display("%d Tests completed successfully", testnum);
|
$display("%d Tests completed successfully", testnum);
|
||||||
$stop;
|
$stop;
|
||||||
@ -119,12 +154,14 @@ module testbench;
|
|||||||
begin
|
begin
|
||||||
req <= #5 0;
|
req <= #5 0;
|
||||||
correctr = nextr;
|
correctr = nextr;
|
||||||
|
$display("pre increment");
|
||||||
testnum = testnum+1;
|
testnum = testnum+1;
|
||||||
Vec = Tests[testnum];
|
|
||||||
$display("a = %h b = %h",a,b);
|
|
||||||
a = Vec[`mema];
|
a = Vec[`mema];
|
||||||
b = Vec[`memb];
|
b = Vec[`memb];
|
||||||
|
Vec = Tests[testnum];
|
||||||
|
$display("a = %h b = %h result = %h",a,b,nextr);
|
||||||
nextr = Vec[`memr];
|
nextr = Vec[`memr];
|
||||||
|
$display("after increment");
|
||||||
end
|
end
|
||||||
end
|
end
|
||||||
|
|
||||||
|
File diff suppressed because it is too large
Load Diff
Loading…
Reference in New Issue
Block a user