Merge branch 'main' of https://github.com/openhwgroup/cvw into dev

sim/sim-testfloat-batch

@@ -4,9 +4,12 @@
 # cmp    - test comparison unit's LT, LE, EQ opperations (fcmp)
 # add    - test addition
 # fma    - test fma
+# mul    - test mult with fma
 # sub    - test subtraction
 # div    - test division
 # sqrt   - test square root
 # all    - test everything
 
-vsim -c -do "do testfloat.do rv64fpquad $1"
+# nowave for 2nd argument supresses wlf files
+
+vsim -c -do "do testfloat.do rv64fpquad $1 $2"

sim/testfloat.do

@@ -29,16 +29,21 @@ vlog +incdir+../config/$1 +incdir+../config/shared ../testbench/testbench-fp.sv
 
 vsim -voptargs=+acc work.testbenchfp -G TEST=$2
 
-view wave
 #-- display input and output signals as hexidecimal values
-#do ./wave-dos/peripheral-waves.do
+if {$3 == "wave"} {
-add log -recursive /*
+    puts "wave output is selected"
-#do wave.do deal with when ready
+    view wave
+    add log -recursive /*
+    do wave-fpu.do
+} elseif {$3 == "nowave"} {
+    puts "No wave output is selected"
+} else {
+    puts "Error with third argument"
+    exit 2
+}
   
-do wave-fpu.do
 
 #-- Run the Simulation 
-#run 3600 
 run -all
 noview testbench-fp.sv
 view wave

testbench/testbench-fp.sv

@@ -1,4 +1,4 @@
-<///////////////////////////////////////////
+///////////////////////////////////////////
 //
 // Written: me@KatherineParry.com
 // Modified: 7/5/2022
@@ -26,10 +26,6 @@
 `include "wally-config.vh"
 `include "tests-fp.vh"
 
-// steps to run FMA Tests
-//    1) create test vectors in riscv-wally/Tests/fp with: ./run-all.sh
-//    2) go to cvw/testbench/fp/Tests
-//    3) run ./sim-fma-batch
 module testbenchfp;
   parameter TEST="none";
 
@@ -52,6 +48,7 @@ module testbenchfp;
   logic [2:0]                  UnitVal, OpCtrlVal, FrmVal; // value of the currnet Unit/OpCtrl/FrmVal
   logic                        WriteIntVal;                // value of the current WriteInt
   logic [`FLEN-1:0]            X, Y, Z;                    // inputs read from TestFloat
+  logic [`FLEN-1:0] 	       XPostBox;                   // inputs read from TestFloat
   logic [`XLEN-1:0]            SrcA;                       // integer input
   logic [`FLEN-1:0]	       Ans;                        // correct answer from TestFloat
   logic [`FLEN-1:0]	       Res;                        // result from other units
@@ -102,6 +99,15 @@ module testbenchfp;
   logic [`NE+1:0]              DivCalcExp;
   logic                        divsqrtop;
 
+   // Missing logic vectors fdivsqrt
+   logic [2:0]                 Funct3E;
+   logic [2:0]                 Funct3M;
+   logic                       FlushE;
+   logic                       IFDivStartE, FDivDoneE;
+   logic [`NE+1:0]             QeM;
+   logic [`DIVb:0]             QmM;
+   logic [`XLEN-1:0]           FIntDivResultM;   
+
 
   ///////////////////////////////////////////////////////////////////////////////////////////////
 
@@ -148,7 +154,8 @@ module testbenchfp;
             end
          end
       end 
-      if (TEST === "cvtfp" | TEST === "all") begin  // if the floating-point conversions are being tested
+      // if the floating-point conversions are being tested          
+      if (TEST === "cvtfp" | TEST === "all") begin  
         if(`D_SUPPORTED) begin // if double precision is supported
           // add the 128 <-> 64 bit conversions to the to-be-tested list
           Tests = {Tests, f128f64cvt};
@@ -571,38 +578,23 @@ module testbenchfp;
       end
       if (TEST === "div"   | TEST === "all") begin // if division is being tested
         // add the correct tests/op-ctrls/unit/fmt to their lists
-        Tests = {f16div, Tests};
+        Tests = {Tests, f16div};
-        OpCtrl = {`DIV_OPCTRL, OpCtrl};
-        WriteInt = {1'b0, WriteInt};
-        for(int i = 0; i<5; i++) begin
-          Unit = {`DIVUNIT, Unit};
-          Fmt = {2'b10, Fmt};
-        end
-        /* Tests = {Tests, f16div};
         OpCtrl = {OpCtrl, `DIV_OPCTRL};
         WriteInt = {WriteInt, 1'b0};
         for(int i = 0; i<5; i++) begin
           Unit = {Unit, `DIVUNIT};
           Fmt = {Fmt, 2'b10};
-        end */
+        end
       end
       if (TEST === "sqrt"  | TEST === "all") begin // if sqrt is being tested
         // add the correct tests/op-ctrls/unit/fmt to their lists
-        // reverse order
+        Tests = {Tests, f16sqrt};
-        Tests = {f16sqrt, Tests};
-        OpCtrl = {`SQRT_OPCTRL, OpCtrl};
-        WriteInt = {1'b0, WriteInt};
-        for(int i = 0; i<5; i++) begin
-          Unit = {`DIVUNIT, Unit};
-          Fmt = {2'b10, Fmt};
-        end
-/*        Tests = {Tests, f16sqrt};
         OpCtrl = {OpCtrl, `SQRT_OPCTRL};
         WriteInt = {WriteInt, 1'b0};
         for(int i = 0; i<5; i++) begin
           Unit = {Unit, `DIVUNIT};
           Fmt = {Fmt, 2'b10};
-        end */
+        end 
       end
       if (TEST === "fma"   | TEST === "all") begin // if fma is being tested
         Tests = {Tests, f16fma};
@@ -666,8 +658,7 @@ module testbenchfp;
                            .XSubnorm, .ZSubnorm, 
                            .XZero, .YZero, .ZZero,
                            .XInf, .YInf, .ZInf, .XExpMax,
-                                    .X, .Y, .Z);
+                           .X, .Y, .Z, .XPostBox);
-
 
 
   ///////////////////////////////////////////////////////////////////////////////////////////////
@@ -713,11 +704,16 @@ module testbenchfp;
                 .XNaN, .YNaN, .XSNaN, .YSNaN, .X, .Y, .CmpNV(CmpFlg[4]), .CmpFpRes(FpCmpRes));
   end
   if (TEST === "div" | TEST === "sqrt" | TEST === "all") begin: fdivsqrt
-    fdivsqrt fdivsqrt(.clk, .reset, .XsE(Xs), .FmtE(ModFmt), .XmE(Xm), .YmE(Ym), .XeE(Xe), .YeE(Ye), .SqrtE(OpCtrlVal[0]), .SqrtM(OpCtrlVal[0]),
+     fdivsqrt fdivsqrt(.clk, .reset, .XsE(Xs), .FmtE(ModFmt), .XmE(Xm), .YmE(Ym), 
-                    .XInfE(XInf), .YInfE(YInf), .XZeroE(XZero), .YZeroE(YZero), .XNaNE(XNaN), .YNaNE(YNaN), 
+		       .XeE(Xe), .YeE(Ye), .SqrtE(OpCtrlVal[0]), .SqrtM(OpCtrlVal[0]),
-                    .FDivStartE(DivStart), .IDivStartE(1'b0), .MDUE(1'b0), .W64E(1'b0),
+                       .XInfE(XInf), .YInfE(YInf), .XZeroE(XZero), .YZeroE(YZero), 
-                    .StallM(1'b0), .DivSM(DivSticky), .FDivBusyE, .QeM(DivCalcExp),
+		       .XNaNE(XNaN), .YNaNE(YNaN), 
-                    .QmM(Quot));
+                       .FDivStartE(DivStart), .IDivStartE(1'b0), .W64E(1'b0),
+                       .StallM(1'b0), .DivStickyM(DivSticky), .FDivBusyE, .QeM(DivCalcExp),
+                       .QmM(Quot),
+                       .FlushE(1'b0), .ForwardedSrcAE('0), .ForwardedSrcBE('0), .Funct3M(Funct3M),
+                       .Funct3E(Funct3E), .IntDivE(1'b0), .FIntDivResultM(FIntDivResultM),
+                       .FDivDoneE(FDivDoneE), .IFDivStartE(IFDivStartE));
   end
 
   assign CmpFlg[3:0] = 0;
@@ -727,6 +723,16 @@ module testbenchfp;
     clk = 1; #5; clk = 0; #5;
   end
 
+  // Provide reset for divsqrt to reset state to IDLE
+  // Previous version did not initiate a divide due to missing state
+  // information.  This starts the FSM by putting the fdivsqrt into
+  // the IDLE state.
+  initial
+  begin
+    #0 reset = 1'b1;
+    #25 reset = 1'b0;     
+  end  
+  
 ///////////////////////////////////////////////////////////////////////////////////////////////
 
 //          |||||      |||  ||||||||||  |||||      |||
@@ -738,7 +744,7 @@ module testbenchfp;
 
 ///////////////////////////////////////////////////////////////////////////////////////////////
 
-  //Check if the correct answer and result is a NaN
+  // Check if the correct answer and result is a NaN
   always_comb begin
     if(UnitVal === `CVTINTUNIT | UnitVal === `CMPUNIT) begin
       // an integer output can't be a NaN
@@ -809,7 +815,7 @@ end
   logic ResMatch, FlagMatch, CheckNow;
 
 always @(posedge clk) 
-  OldFDivBusyE = FDivBusyE;
+  OldFDivBusyE = FDivDoneE;
 
 // check results on falling edge of clk
 always @(negedge clk) begin
@@ -912,9 +918,15 @@ always @(negedge clk) begin
       $stop;
     end
 
-    if(~(FDivBusyE|DivStart)|(UnitVal != `DIVUNIT)) VectorNum += 1; // increment the vector
+    // Add extra clock cycles in beginning for fdivsqrt to adequate reset state
+    if(~(FDivBusyE|DivStart)|(UnitVal != `DIVUNIT)) begin
+       repeat (12)
+	 @(posedge clk);
+       if (reset != 1'b1)
+	 VectorNum += 1; // increment the vector
+    end
    
-    if (TestVectors[VectorNum][0] === 1'bx & Tests[TestNum] !== "") begin // if reached the end of file
+    if (TestVectors[VectorNum][0] === 1'bx & Tests[TestNum] !== "") begin // if reached the eof
 
       // increment the test
       TestNum += 1;
@@ -944,8 +956,6 @@ always @(negedge clk) begin
 endmodule
 
 
-
-
 module readvectors (
   input logic                clk,
   input logic [`FLEN*4+7:0]  TestVector,
@@ -968,7 +978,7 @@ module readvectors (
   output logic               XInf, YInf, ZInf,    // is XYZ infinity
   output logic               XExpMax,
   output logic               DivStart,
-  output logic [`FLEN-1:0] X, Y, Z
+  output logic [`FLEN-1:0]   X, Y, Z, XPostBox
 );
   logic XEn, YEn, ZEn;
 
@@ -1331,5 +1341,5 @@ module readvectors (
   unpack unpack(.X, .Y, .Z, .Fmt(ModFmt), .Xs, .Ys, .Zs, .Xe, .Ye, .Ze,
                 .Xm, .Ym, .Zm, .XNaN, .YNaN, .ZNaN, .XSNaN, .YSNaN, .ZSNaN,
                 .XSubnorm, .XZero, .YZero, .ZZero, .XInf, .YInf, .ZInf,
-                .XEn, .YEn, .ZEn, .XExpMax);
+                .XEn, .YEn, .ZEn, .XExpMax, .XPostBox);
 endmodule

testbench/tests-fp.vh

@@ -238,7 +238,6 @@ string f128rv32cvtint[] = '{
 	"f128_to_i32_rnm.tv"
 };
 
-
 string f32f16cvt[] = '{
 	"f32_to_f16_rne.tv",
 	"f32_to_f16_rz.tv",
@@ -291,7 +290,6 @@ string f64f32cvt[] = '{
 	"f32_to_f64_rnm.tv"
 };
 
-
 string f128f32cvt[] = '{
 	"f128_to_f32_rne.tv",
 	"f128_to_f32_rz.tv",
@@ -305,7 +303,6 @@ string f128f32cvt[] = '{
 	"f32_to_f128_rnm.tv"
 };
 
-
 string f128f64cvt[] = '{
 	"f128_to_f64_rne.tv",
 	"f128_to_f64_rz.tv",