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hptw cleanup for synthesis

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David Harris 2022-02-28 05:54:34 +00:00
parent 9b4d6427f4
commit 3a43450ac9
1 changed files with 3 additions and 3 deletions
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6
pipelined/src/mmu/hptw.sv
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@ -124,11 +124,11 @@ module hptw
assign {Dirty, Accessed} = PTE[7:6];
assign WriteAccess = (MemRWM[0] | |AtomicM);
assign SetDirty = ~Dirty & & DTLBWalk & WriteAccess;
assign WriteAccess = MemRWM[0] | (|AtomicM);
assign SetDirty = ~Dirty & DTLBWalk & WriteAccess;
assign ReadAccess = MemRWM[1];
assign EffectivePrivilegeMode = (DTLBWalk == 0) ? PrivilegeModeW : (STATUS_MPRV ? STATUS_MPP : PrivilegeModeW); // DTLB uses MPP mode when MPRV is 1
assign EffectivePrivilegeMode = DTLBWalk ? (STATUS_MPRV ? STATUS_MPP : PrivilegeModeW) : PrivilegeModeW; // DTLB uses MPP mode when MPRV is 1
assign ImproperPrivilege = ((EffectivePrivilegeMode == `U_MODE) & ~PTE_U) |
((EffectivePrivilegeMode == `S_MODE) & PTE_U & (~STATUS_SUM & DTLBWalk));