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Slight tweaks to synthDC for library variables

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This commit is contained in:
James Stine 2022-02-10 17:56:27 -06:00
parent 39be787821
commit 39fd199538
2 changed files with 7 additions and 10 deletions
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2
synthDC/.synopsys_dc.setup
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@ -12,7 +12,7 @@ if { [info exists ::env(RISCV)] } {
} }
if {$tech == "sky130"} { if {$tech == "sky130"} {
set s8lib ../addins/sky130_osu_sc_t12/12T_ms/lib/ set s8lib $timing_lib/sky130_osu_sc_t12/12T_ms/lib/
lappend search_path $s8lib lappend search_path $s8lib
} elseif {$tech == "sky90"} { } elseif {$tech == "sky90"} {
set s9lib $timing_lib/sky90/tech_files/ set s9lib $timing_lib/sky90/tech_files/

15
synthDC/README.md
View File

@ -16,21 +16,18 @@ FREQ
Frequency in MHz. Default is 500 Frequency in MHz. Default is 500
CONFIG CONFIG
The wally configuration file. Default is rv32e. The Wally configuration file. The default is rv32e.
Examples. Examples: rv32e, rv64gc, rv32gc
rv32e
rv64gc
rv32gc
TECH TECH
The target standard cell library. Default is 130. The target standard cell library. The default is sky130.
sky90: skywater 90nm TT 25C sky90: skywater 90nm TT 25C
sky130: skywater 130nm TT 25C sky130: skywater 130nm TT 25C
SAIFPOWER SAIFPOWER
Controls if power analysis is driven by switching factor or RTL modelsim simulation. Controls if power analysis is driven by switching factor or
When enabled requires a saif file named power.saif. RTL modelsim simulation. When enabled requires a saif file
Default is 0. named power.saif. The default is 0.
0: switching factor power analysis 0: switching factor power analysis
1: RTL simulation driven power analysis. 1: RTL simulation driven power analysis.