Fixed PMP issue 132. Updated tests to initialize PMP before using. Needs to remake tests

src/mmu/pmpadrdec.sv

@@ -38,7 +38,7 @@ module pmpadrdec (
   input  logic [`PA_BITS-3:0]      PMPAdr,
   input  logic                  PAgePMPAdrIn,
   output logic                  PAgePMPAdrOut,
-  output logic                  Match, Active, 
+  output logic                  Match, 
   output logic                  L, X, W, R
 );
   
@@ -84,7 +84,6 @@ module pmpadrdec (
   assign X = PMPCfg[2];
   assign W = PMPCfg[1];
   assign R = PMPCfg[0];
-  assign Active = |PMPCfg[4:3];
 
   // known bug: The size of the access is not yet checked.  For example, if an NA4 entry matches 0xC-0xF and the system
   // attempts an 8-byte access to 0x8, the access should fail (see page 60 of privileged specification 20211203). This

src/mmu/pmpchecker.sv

@@ -53,7 +53,6 @@ module pmpchecker (
   logic                    EnforcePMP; // should PMP be checked in this privilege level
   logic [`PMP_ENTRIES-1:0] Match;      // physical address matches one of the pmp ranges
   logic [`PMP_ENTRIES-1:0] FirstMatch; // onehot encoding for the first pmpaddr to match the current address.
-  logic [`PMP_ENTRIES-1:0] Active;     // PMP register i is non-null
   logic [`PMP_ENTRIES-1:0] L, X, W, R; // PMP matches and has flag set
   logic [`PMP_ENTRIES-1:0] PAgePMPAdr; // for TOR PMP matching, PhysicalAddress > PMPAdr[i]
 
@@ -64,14 +63,12 @@ module pmpchecker (
       .PMPAdr(PMPADDR_ARRAY_REGW),
       .PAgePMPAdrIn({PAgePMPAdr[`PMP_ENTRIES-2:0], 1'b1}),
       .PAgePMPAdrOut(PAgePMPAdr),
-      .Match, .Active, .L, .X, .W, .R);
+      .Match, .L, .X, .W, .R);
 
   priorityonehot #(`PMP_ENTRIES) pmppriority(.a(Match), .y(FirstMatch)); // combine the match signal from all the adress decoders to find the first one that matches.
 
   // Only enforce PMP checking for S and U modes or in Machine mode when L bit is set in selected region
-  assign EnforcePMP = (PrivilegeModeW == `M_MODE) ? |(L & FirstMatch) : |Active; 
+  assign EnforcePMP = (PrivilegeModeW != `M_MODE) | |(L & FirstMatch); // *** switch to this logic when PMP is initialized for non-machine mode
-//  assign EnforcePMP = (PrivilegeModeW != `M_MODE) | |(L & FirstMatch); // *** switch to this logic when PMP is initialized for non-machine mode
-//  *** remove unused Active lines from pmpadrdecs
 
   assign PMPInstrAccessFaultF     = EnforcePMP & ExecuteAccessF & ~|(X & FirstMatch) ;
   assign PMPStoreAmoAccessFaultM  = EnforcePMP & WriteAccessM   & ~|(W & FirstMatch) ;

tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-TEST-LIB-32.h

@@ -55,6 +55,12 @@ RVTEST_CODE_BEGIN
     csrw sscratch, sp
     la sp, stack_top
 
+    // set up PMP so user and supervisor mode can access full address space
+    csrw pmpcfg0, 0xF   # configure PMP0 to TOR RWX
+    li t0, 0xFFFFFFFF   
+    csrw pmpaddr0, t0   # configure PMP0 top of range to 0xFFFFFFFF to allow all 32-bit addresses
+
+
 .endm
 
 // Code to trigger traps goes here so we have consistent mtvals for instruction adresses

tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-TEST-LIB-64.h

@@ -57,6 +57,11 @@ RVTEST_CODE_BEGIN
     csrw sscratch, sp
     la sp, stack_top
 
+    // set up PMP so user and supervisor mode can access full address space
+    csrw pmpcfg0, 0xF   # configure PMP0 to TOR RWX
+    li t0, 0xFFFFFFFF   
+    csrw pmpaddr0, t0   # configure PMP0 top of range to 0xFFFFFFFF to allow all 32-bit addresses
+
 .endm
 
 // Code to trigger traps goes here so we have consistent mtvals for instruction adresses