Xavi/cvw
1
0
Fork 0
forked from Github_Repos/cvw
Code Issues Pull Requests Packages Projects Releases Wiki Activity

declare memread signal

Browse Source
This commit is contained in:
bbracker 2021-04-05 08:13:01 -04:00
parent a4c3afb847
commit 38017e6aae
1 changed files with 2 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
wally-pipelined/src/uncore/plic.sv
View File

@ -49,7 +49,7 @@ module plic (
localparam N=`PLIC_NUM_SRC; // should not exceed 63; does not inlcude source 0, which does not connect to anything according to spec
logic memwrite, initTrans;
logic memwrite, memread, initTrans;
logic [27:0] entry, entryd;
logic [31:0] Din, Dout;
logic [N:1] requests;