forked from Github_Repos/cvw
declare memread signal
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@ -49,7 +49,7 @@ module plic (
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localparam N=`PLIC_NUM_SRC; // should not exceed 63; does not inlcude source 0, which does not connect to anything according to spec
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localparam N=`PLIC_NUM_SRC; // should not exceed 63; does not inlcude source 0, which does not connect to anything according to spec
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logic memwrite, initTrans;
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logic memwrite, memread, initTrans;
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logic [27:0] entry, entryd;
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logic [27:0] entry, entryd;
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logic [31:0] Din, Dout;
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logic [31:0] Din, Dout;
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logic [N:1] requests;
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logic [N:1] requests;
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@ -167,7 +167,7 @@ module plic (
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`endif
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`endif
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// or temporarily connect them to nothing
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// or temporarily connect them to nothing
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assign requests[3:1] = 3'b0;
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assign requests[3:1] = 3'b0;
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// pending updates
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// pending updates
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// *** verify that this matches the expectations of the things that make requests (in terms of timing, edge-triggered vs level-triggered)
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// *** verify that this matches the expectations of the things that make requests (in terms of timing, edge-triggered vs level-triggered)
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assign nextIntPending = (intPending | (requests & ~intInProgress)) // requests should raise intPending except when their service routine is already in progress
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assign nextIntPending = (intPending | (requests & ~intInProgress)) // requests should raise intPending except when their service routine is already in progress
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