forked from Github_Repos/cvw
Flip-flop clean-up
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a8a5fa4b3c
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@ -119,9 +119,6 @@ module pagetablewalker
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flop #(`XLEN) HPTWPAdrMReg(.clk(clk),
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.d(HPTWPAdrE),
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.q(HPTWPAdrM));
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@ -135,9 +132,9 @@ module pagetablewalker
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assign TranslationVAdr = (SelDataTranslation) ? MemAdrM : PCF;
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assign TranslationVAdr = (SelDataTranslation) ? MemAdrM : PCF;
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assign SelDataTranslation = DTLBMissMQ | DTLBMissM;
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assign SelDataTranslation = DTLBMissMQ | DTLBMissM;
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flopenrc #(1)
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flop #(`XLEN) HPTWPAdrMReg(clk, HPTWPAdrE, HPTWPAdrM);
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DTLBMissMReg(.clk(clk),
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flopenrc #(2) TLBMissMReg(clk, reset, StartWalk | EndWalk, EndWalk, {DTLBMissM, ITLBMissF}, {DTLBMissMQ, ITLBMissFQ});
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.reset(reset),
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/* .reset(reset),
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.en(StartWalk | EndWalk),
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.en(StartWalk | EndWalk),
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.clear(EndWalk),
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.clear(EndWalk),
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.d(DTLBMissM),
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.d(DTLBMissM),
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@ -149,7 +146,7 @@ module pagetablewalker
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.en(StartWalk | EndWalk),
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.en(StartWalk | EndWalk),
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.clear(EndWalk),
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.clear(EndWalk),
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.d(ITLBMissF),
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.d(ITLBMissF),
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.q(ITLBMissFQ));
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.q(ITLBMissFQ)); */
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flopenl #(.TYPE(statetype)) WalkerStateReg(clk, reset, 1'b1, NextWalkerState, IDLE, WalkerState);
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flopenl #(.TYPE(statetype)) WalkerStateReg(clk, reset, 1'b1, NextWalkerState, IDLE, WalkerState);
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flopenl #(.TYPE(statetype)) PreviousWalkerStateReg(clk, reset, 1'b1, WalkerState, IDLE, PreviousWalkerState);
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flopenl #(.TYPE(statetype)) PreviousWalkerStateReg(clk, reset, 1'b1, WalkerState, IDLE, PreviousWalkerState);
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