forked from Github_Repos/cvw
working GPIO interrupt demo
This commit is contained in:
bbracker
parent
e69cc0d23a
commit
368c94d4ff
@ -90,7 +90,8 @@
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`define UART_PRESCALE 1
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`define UART_PRESCALE 1
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// Interrupt configuration
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// Interrupt configuration
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`define PLIC_NUM_SRC 53
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`define PLIC_NUM_SRC 4
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`define PLIC_GPIO_ID 3
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`define PLIC_UART_ID 4
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`define PLIC_UART_ID 4
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/* verilator lint_off STMTDLY */
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/* verilator lint_off STMTDLY */
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@ -82,7 +82,7 @@
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// Test modes
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// Test modes
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// Tie GPIO outputs back to inputs
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// Tie GPIO outputs back to inputs
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`define GPIO_LOOPBACK_TEST 0
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`define GPIO_LOOPBACK_TEST 1
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// Busybear special CSR config to match OVPSim
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// Busybear special CSR config to match OVPSim
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`define OVPSIM_CSR_CONFIG 0
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`define OVPSIM_CSR_CONFIG 0
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@ -92,6 +92,7 @@
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// Interrupt configuration
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// Interrupt configuration
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`define PLIC_NUM_SRC 4
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`define PLIC_NUM_SRC 4
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`define PLIC_GPIO_ID 3
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`define PLIC_UART_ID 4
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`define PLIC_UART_ID 4
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/* verilator lint_off STMTDLY */
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/* verilator lint_off STMTDLY */
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@ -58,14 +58,16 @@ add wave -divider
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add wave -divider
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add wave -divider
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# peripherals
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# peripherals
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add wave -hex /testbench/dut/hart/ebu/*
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add wave -hex /testbench/dut/uncore/gpio/*
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add wave -divider
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add wave -hex /testbench/dut/uncore/uart/u/*
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add wave -divider
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add wave -divider
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add wave -hex /testbench/dut/uncore/plic/*
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add wave -hex /testbench/dut/uncore/plic/*
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add wave -hex /testbench/dut/uncore/plic/intPriority
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add wave -hex /testbench/dut/uncore/plic/intPriority
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add wave -hex /testbench/dut/uncore/plic/pendingArray
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add wave -hex /testbench/dut/uncore/plic/pendingArray
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add wave -divider
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add wave -divider
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add wave -hex /testbench/dut/uncore/uart/u/*
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add wave -divider
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add wave -hex /testbench/dut/hart/ebu/*
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add wave -divider
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add wave -divider
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add wave -divider
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# everything else
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# everything else
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@ -49,7 +49,6 @@ module ahblite (
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// Signals from MMU
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// Signals from MMU
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input logic [`XLEN-1:0] MMUPAdr,
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input logic [`XLEN-1:0] MMUPAdr,
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input logic MMUTranslate, MMUTranslationComplete,
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input logic MMUTranslate, MMUTranslationComplete,
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input logic TrapM,
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output logic [`XLEN-1:0] MMUReadPTE,
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output logic [`XLEN-1:0] MMUReadPTE,
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output logic MMUReady,
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output logic MMUReady,
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// Return from bus
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// Return from bus
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@ -131,6 +130,7 @@ module ahblite (
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else NextBusState = IDLE; // if (InstrReadF still high)
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else NextBusState = IDLE; // if (InstrReadF still high)
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INSTRREADC: if (~HREADY) NextBusState = INSTRREADC; // "C" for "competing", meaning please don't mess up the memread in the W stage.
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INSTRREADC: if (~HREADY) NextBusState = INSTRREADC; // "C" for "competing", meaning please don't mess up the memread in the W stage.
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else NextBusState = IDLE;
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else NextBusState = IDLE;
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default: NextBusState = IDLE;
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endcase
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endcase
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// stall signals
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// stall signals
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@ -138,11 +138,11 @@ module ahblite (
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// since translation might not be complete.
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// since translation might not be complete.
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assign #2 DataStall = ((NextBusState == MEMREAD) || (NextBusState == MEMWRITE) ||
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assign #2 DataStall = ((NextBusState == MEMREAD) || (NextBusState == MEMWRITE) ||
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(NextBusState == ATOMICREAD) || (NextBusState == ATOMICWRITE) ||
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(NextBusState == ATOMICREAD) || (NextBusState == ATOMICWRITE) ||
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(NextBusState == MMUTRANSLATE) || (MMUTranslate && ~MMUTranslationComplete)); // && ~TrapM
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(NextBusState == MMUTRANSLATE) || (MMUTranslate && ~MMUTranslationComplete));
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// *** Could get finer grained stalling if we distinguish between MMU
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// *** Could get finer grained stalling if we distinguish between MMU
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// instruction address translation and data address translation
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// instruction address translation and data address translation
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assign #1 InstrStall = ((NextBusState == INSTRREAD) || (NextBusState == INSTRREADC) ||
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assign #1 InstrStall = ((NextBusState == INSTRREAD) || (NextBusState == INSTRREADC) ||
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(NextBusState == MMUTRANSLATE) || (MMUTranslate && ~MMUTranslationComplete)); // && ~TrapM
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(NextBusState == MMUTRANSLATE) || (MMUTranslate && ~MMUTranslationComplete));
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// bus outputs
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// bus outputs
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assign #1 GrantData = (NextBusState == MEMREAD) || (NextBusState == MEMWRITE) ||
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assign #1 GrantData = (NextBusState == MEMREAD) || (NextBusState == MEMWRITE) ||
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@ -2,7 +2,7 @@
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// gpio.sv
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// gpio.sv
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//
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//
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// Written: David_Harris@hmc.edu 14 January 2021
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// Written: David_Harris@hmc.edu 14 January 2021
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// Modified:
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// Modified: bbracker@hmc.edu 15 Apr. 2021
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//
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//
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// Purpose: General Purpose I/O peripheral
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// Purpose: General Purpose I/O peripheral
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// See FE310-G002-Manual-v19p05 for specifications
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// See FE310-G002-Manual-v19p05 for specifications
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@ -38,84 +38,134 @@ module gpio (
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output logic [`XLEN-1:0] HREADGPIO,
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output logic [`XLEN-1:0] HREADGPIO,
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output logic HRESPGPIO, HREADYGPIO,
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output logic HRESPGPIO, HREADYGPIO,
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input logic [31:0] GPIOPinsIn,
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input logic [31:0] GPIOPinsIn,
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output logic [31:0] GPIOPinsOut, GPIOPinsEn);
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output logic [31:0] GPIOPinsOut, GPIOPinsEn,
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output logic GPIOIntr);
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logic [31:0] INPUT_VAL, INPUT_EN, OUTPUT_EN, OUTPUT_VAL;
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logic [31:0] input0d, input1d, input2d, input3d;
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logic [31:0] input_val, input_en, output_en, output_val;
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logic [31:0] rise_ie, rise_ip, fall_ie, fall_ip, high_ie, high_ip, low_ie, low_ip;
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logic [7:0] entry, HADDRd;
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logic initTrans, memread, memwrite;
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logic initTrans, memread, memwrite;
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logic [7:0] entry, entryd, HADDRd;
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logic [31:0] Din, Dout;
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// AHB I/O
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assign entry = {HADDR[7:2],2'b0};
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assign initTrans = HREADY & HSELGPIO & (HTRANS != 2'b00);
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assign initTrans = HREADY & HSELGPIO & (HTRANS != 2'b00);
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assign memread = initTrans & ~HWRITE;
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// Control Signals
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// entryd and memwrite are delayed by a cycle because AHB controller waits a cycle before outputting write data
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flopenr #(1) memreadreg(HCLK, ~HRESETn, initTrans, ~HWRITE, memread);
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flopr #(1) memwriteflop(HCLK, ~HRESETn, initTrans & HWRITE, memwrite);
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flopenr #(1) memwritereg(HCLK, ~HRESETn, initTrans, HWRITE, memwrite);
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flopr #(8) entrydflop(HCLK, ~HRESETn, entry, entryd);
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flopenr #(8) haddrreg(HCLK, ~HRESETn, initTrans, HADDR, HADDRd);
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// Response Signals
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assign HRESPGPIO = 0; // OK
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assign HRESPGPIO = 0; // OK
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assign HREADYGPIO = 1; // never ask for wait states
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assign HREADYGPIO = 1'b1; // GPIO never takes >1 cycle to respond
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// word aligned reads
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// account for subword read/write circuitry
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generate
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// -- Note GPIO registers are 32 bits no matter what; access them with LW SW.
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if (`XLEN==64)
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// (At least that's what I think when FE310 spec says "only naturally aligned 32-bit accesses are supported")
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assign #2 entry = {HADDR[7:3], 3'b000};
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else
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assign #2 entry = {HADDR[7:2], 2'b00};
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endgenerate
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generate
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if (`GPIO_LOOPBACK_TEST) // connect OUT to IN for loopback testing
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assign INPUT_VAL = GPIOPinsOut & INPUT_EN & OUTPUT_EN;
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else
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assign INPUT_VAL = GPIOPinsIn & INPUT_EN;
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endgenerate
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assign GPIOPinsOut = OUTPUT_VAL;
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assign GPIOPinsEn = OUTPUT_EN;
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// register access
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generate
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generate
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if (`XLEN == 64) begin
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if (`XLEN == 64) begin
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always_ff @(posedge HCLK) begin
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always_comb
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case(entry)
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if (entryd[2]) begin
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8'h00: HREADGPIO <= {INPUT_EN, INPUT_VAL};
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Din = HWDATA[63:32];
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8'h08: HREADGPIO <= {OUTPUT_VAL, OUTPUT_EN};
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HREADGPIO = {Dout,32'b0};
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8'h40: HREADGPIO <= 0; // OUT_XOR reads as 0
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end else begin
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default: HREADGPIO <= 0;
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Din = HWDATA[31:0];
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endcase
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HREADGPIO = {32'b0,Dout};
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end
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always_ff @(posedge HCLK or negedge HRESETn)
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if (~HRESETn) begin
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INPUT_EN <= 0;
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OUTPUT_EN <= 0;
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OUTPUT_VAL <= 0; // spec indicates synchronous reset (software control)
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end else if (memwrite) begin
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if (entry == 8'h00) INPUT_EN <= HWDATA[63:32];
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if (entry == 8'h08) {OUTPUT_VAL, OUTPUT_EN} <= HWDATA;
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if (entry == 8'h40) OUTPUT_VAL <= OUTPUT_VAL ^ HWDATA[31:0]; // OUT_XOR
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end
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end
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end else begin // 32-bit
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end else begin // 32-bit
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always_ff @(posedge HCLK) begin
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always_comb begin
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case(entry)
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Din = HWDATA[31:0];
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8'h00: HREADGPIO <= INPUT_VAL;
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HREADGPIO = Dout;
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8'h04: HREADGPIO <= INPUT_EN;
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8'h08: HREADGPIO <= OUTPUT_EN;
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8'h0C: HREADGPIO <= OUTPUT_VAL;
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8'h40: HREADGPIO <= 0; // OUT_XOR reads as 0
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default: HREADGPIO <= 0;
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endcase
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end
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always_ff @(posedge HCLK or negedge HRESETn)
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if (~HRESETn) begin
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INPUT_EN <= 0;
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OUTPUT_EN <= 0;
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end else if (memwrite) begin
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if (entry == 8'h04) INPUT_EN <= HWDATA;
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if (entry == 8'h08) OUTPUT_EN <= HWDATA;
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if (entry == 8'h0C) OUTPUT_VAL <= HWDATA;
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if (entry == 8'h40) OUTPUT_VAL <= OUTPUT_VAL ^ HWDATA; // OUT_XOR
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end
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end
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end
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end
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endgenerate
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endgenerate
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// register access
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always_ff @(posedge HCLK, negedge HRESETn) begin
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// reads
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case(entry)
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8'h00: Dout <= #1 input_val;
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8'h04: Dout <= #1 input_en;
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8'h08: Dout <= #1 output_en;
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8'h0C: Dout <= #1 output_val;
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8'h18: Dout <= #1 rise_ie;
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8'h1C: Dout <= #1 rise_ip;
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8'h20: Dout <= #1 fall_ie;
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8'h24: Dout <= #1 fall_ip;
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8'h28: Dout <= #1 high_ie;
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8'h2C: Dout <= #1 high_ip;
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8'h30: Dout <= #1 low_ie;
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8'h34: Dout <= #1 low_ip;
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8'h40: Dout <= #1 0; // OUT_XOR reads as 0
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default: Dout <= #1 0;
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endcase
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// writes
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if (~HRESETn) begin
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// asynch reset
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input_en <= 0;
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output_en <= 0;
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// *** synch reset not yet implemented
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output_val <= #1 0;
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rise_ie <= #1 0;
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rise_ip <= #1 0;
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fall_ie <= #1 0;
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fall_ip <= #1 0;
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high_ie <= #1 0;
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high_ip <= #1 0;
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low_ie <= #1 0;
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low_ip <= #1 0;
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end else if (memwrite)
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// According to FE310 spec: Once the interrupt is pending, it will remain set until a 1 is written to the *_ip register at that bit.
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case(entryd)
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8'h04: input_en <= #1 Din;
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8'h08: output_en <= #1 Din;
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8'h0C: output_val <= #1 Din;
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8'h18: rise_ie <= #1 Din;
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8'h1C: rise_ip <= #1 rise_ip & ~Din;
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8'h20: fall_ie <= #1 Din;
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8'h24: fall_ip <= #1 fall_ip & ~Din;
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8'h28: high_ie <= #1 Din;
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8'h2C: high_ip <= #1 high_ip & ~Din;
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8'h30: low_ie <= #1 Din;
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8'h34: low_ip <= #1 low_ip & ~Din;
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8'h40: output_val <= #1 output_val ^ Din; // OUT_XOR
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endcase
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end
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// chip i/o
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generate
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if (`GPIO_LOOPBACK_TEST) // connect OUT to IN for loopback testing
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assign input0d = GPIOPinsOut & input_en & output_en;
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else
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assign input0d = GPIOPinsIn & input_en;
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endgenerate
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// *** this costs lots of flops; I suspect they don't need to be resettable, do they?
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flop #(32) sync1(HCLK,input0d,input1d);
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flop #(32) sync2(HCLK,input1d,input2d);
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flop #(32) sync3(HCLK,input2d,input3d);
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assign input_val = input3d;
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assign GPIOPinsOut = output_val;
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assign GPIOPinsEn = output_en;
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// interrupts
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always_ff @(posedge HCLK) begin
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if (memwrite && (entryd == 8'h1C))
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rise_ip <= rise_ip & ~Din | (input2d & ~input3d);
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else
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rise_ip <= rise_ip | (input2d & ~input3d);
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if (memwrite && (entryd == 8'h24))
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fall_ip <= fall_ip & ~Din | (~input2d & input3d);
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else
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fall_ip <= fall_ip | (~input2d & input3d);
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if (memwrite && (entryd == 8'h2C))
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high_ip <= high_ip & ~Din | input3d;
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else
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high_ip <= high_ip | input3d;
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if (memwrite && (entryd == 8'h34))
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low_ip <= low_ip & ~Din | ~input3d;
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else
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low_ip <= low_ip | ~input3d;
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end
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assign GPIOIntr = |{(rise_ip & rise_ie),(fall_ip & fall_ip),(high_ip & high_ie),(low_ip & low_ie)};
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endmodule
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endmodule
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@ -37,12 +37,12 @@
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module plic (
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module plic (
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input logic HCLK, HRESETn,
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input logic HCLK, HRESETn,
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input logic HSELPLIC,
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input logic HSELPLIC,
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input logic [27:0] HADDR,
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input logic [27:0] HADDR, // *** could factor out entryd into HADDRd at the level of uncore
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input logic HWRITE,
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input logic HWRITE,
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input logic HREADY,
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input logic HREADY,
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input logic [1:0] HTRANS,
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input logic [1:0] HTRANS,
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input logic [`XLEN-1:0] HWDATA,
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input logic [`XLEN-1:0] HWDATA,
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input logic UARTIntr,
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input logic UARTIntr,GPIOIntr,
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output logic [`XLEN-1:0] HREADPLIC,
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output logic [`XLEN-1:0] HREADPLIC,
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output logic HRESPPLIC, HREADYPLIC,
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output logic HRESPPLIC, HREADYPLIC,
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output logic ExtIntM);
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output logic ExtIntM);
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@ -77,7 +77,7 @@ module plic (
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// account for subword read/write circuitry
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// account for subword read/write circuitry
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// -- Note PLIC registers are 32 bits no matter what; access them with LW SW.
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// -- Note PLIC registers are 32 bits no matter what; access them with LW SW.
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generate
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generate // *** add ld, sd functionality
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if (`XLEN == 64) begin
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if (`XLEN == 64) begin
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always_comb
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always_comb
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if (entryd[2]) begin
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if (entryd[2]) begin
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@ -162,11 +162,15 @@ module plic (
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endgenerate
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endgenerate
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// connect sources to requests
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// connect sources to requests
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`ifdef PLIC_UART_ID
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always_comb begin
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assign requests[`PLIC_UART_ID] = UARTIntr;
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requests = {N{1'b0}};
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`ifdef PLIC_GPIO_ID
|
||||||
|
requests[`PLIC_GPIO_ID] = GPIOIntr;
|
||||||
`endif
|
`endif
|
||||||
// or temporarily connect them to nothing
|
`ifdef PLIC_UART_ID
|
||||||
assign requests[3:1] = 3'b0;
|
requests[`PLIC_UART_ID] = UARTIntr;
|
||||||
|
`endif
|
||||||
|
end
|
||||||
|
|
||||||
// pending updates
|
// pending updates
|
||||||
// *** verify that this matches the expectations of the things that make requests (in terms of timing, edge-triggered vs level-triggered)
|
// *** verify that this matches the expectations of the things that make requests (in terms of timing, edge-triggered vs level-triggered)
|
||||||
|
|||||||
@ -1,325 +0,0 @@
|
|||||||
///////////////////////////////////////////
|
|
||||||
// plic_temp.sv
|
|
||||||
//
|
|
||||||
// This was made to provide a register interface to busybear. I think we'll end up replacing it with our more configurable plic.
|
|
||||||
//
|
|
||||||
// Written: bbracker@hmc.edu 18 January 2021
|
|
||||||
// Modified:
|
|
||||||
//
|
|
||||||
// Purpose: Platform-Level Interrupt Controller
|
|
||||||
// See FU540-C000-Manual-v1p0 for specifications
|
|
||||||
// *** we might want to add support for FE310-G002-Manual-v19p05 version
|
|
||||||
//
|
|
||||||
// A component of the Wally configurable RISC-V project.
|
|
||||||
//
|
|
||||||
// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
|
|
||||||
//
|
|
||||||
// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
|
|
||||||
// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy,
|
|
||||||
// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software
|
|
||||||
// is furnished to do so, subject to the following conditions:
|
|
||||||
//
|
|
||||||
// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
|
|
||||||
//
|
|
||||||
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
|
|
||||||
// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
|
|
||||||
// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
|
|
||||||
// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
|
||||||
///////////////////////////////////////////
|
|
||||||
|
|
||||||
`include "wally-config.vh"
|
|
||||||
|
|
||||||
module plic_temp (
|
|
||||||
input logic HCLK, HRESETn,
|
|
||||||
input logic HSELPLIC,
|
|
||||||
input logic [27:0] HADDR,
|
|
||||||
input logic HWRITE,
|
|
||||||
input logic [`XLEN-1:0] HWDATA,
|
|
||||||
output logic [`XLEN-1:0] HREADPLIC,
|
|
||||||
output logic HRESPPLIC, HREADYPLIC);
|
|
||||||
|
|
||||||
logic memread, memwrite;
|
|
||||||
parameter numSrc = 53;
|
|
||||||
logic [2:0] intPriority [numSrc:1];
|
|
||||||
logic [2:0] intThreshold;
|
|
||||||
logic [numSrc:1] intPending, intEn;
|
|
||||||
logic [31:0] intClaim;
|
|
||||||
logic [27:0] entry;
|
|
||||||
|
|
||||||
// AHB I/O
|
|
||||||
assign memread = HSELPLIC & ~HWRITE;
|
|
||||||
assign memwrite = HSELPLIC & HWRITE;
|
|
||||||
assign HRESPPLIC = 0; // OK
|
|
||||||
assign HREADYPLIC = 1'b1; // will need to be modified if PLIC ever needs more than 1 cycle to do something
|
|
||||||
|
|
||||||
// word aligned reads
|
|
||||||
generate
|
|
||||||
if (`XLEN==64)
|
|
||||||
assign #2 entry = {HADDR[15:3], 3'b000};
|
|
||||||
else
|
|
||||||
assign #2 entry = {HADDR[15:2], 2'b00};
|
|
||||||
endgenerate
|
|
||||||
|
|
||||||
// register access
|
|
||||||
generate
|
|
||||||
if (`XLEN==64) begin
|
|
||||||
always @(posedge HCLK) begin
|
|
||||||
// reading
|
|
||||||
case(entry)
|
|
||||||
// priority assignments
|
|
||||||
28'hc000004: HREADPLIC <= {{(`XLEN-3){1'b0}},intPriority[1]};
|
|
||||||
28'hc000008: HREADPLIC <= {{(`XLEN-3){1'b0}},intPriority[2]};
|
|
||||||
28'hc00000c: HREADPLIC <= {{(`XLEN-3){1'b0}},intPriority[3]};
|
|
||||||
28'hc000010: HREADPLIC <= {{(`XLEN-3){1'b0}},intPriority[4]};
|
|
||||||
28'hc000014: HREADPLIC <= {{(`XLEN-3){1'b0}},intPriority[5]};
|
|
||||||
28'hc000018: HREADPLIC <= {{(`XLEN-3){1'b0}},intPriority[6]};
|
|
||||||
28'hc00001c: HREADPLIC <= {{(`XLEN-3){1'b0}},intPriority[7]};
|
|
||||||
28'hc000020: HREADPLIC <= {{(`XLEN-3){1'b0}},intPriority[8]};
|
|
||||||
28'hc000024: HREADPLIC <= {{(`XLEN-3){1'b0}},intPriority[9]};
|
|
||||||
28'hc000028: HREADPLIC <= {{(`XLEN-3){1'b0}},intPriority[10]};
|
|
||||||
28'hc00002c: HREADPLIC <= {{(`XLEN-3){1'b0}},intPriority[11]};
|
|
||||||
28'hc000030: HREADPLIC <= {{(`XLEN-3){1'b0}},intPriority[12]};
|
|
||||||
28'hc000034: HREADPLIC <= {{(`XLEN-3){1'b0}},intPriority[13]};
|
|
||||||
28'hc000038: HREADPLIC <= {{(`XLEN-3){1'b0}},intPriority[14]};
|
|
||||||
28'hc00003c: HREADPLIC <= {{(`XLEN-3){1'b0}},intPriority[15]};
|
|
||||||
28'hc000040: HREADPLIC <= {{(`XLEN-3){1'b0}},intPriority[16]};
|
|
||||||
28'hc000044: HREADPLIC <= {{(`XLEN-3){1'b0}},intPriority[17]};
|
|
||||||
28'hc000048: HREADPLIC <= {{(`XLEN-3){1'b0}},intPriority[18]};
|
|
||||||
28'hc00004c: HREADPLIC <= {{(`XLEN-3){1'b0}},intPriority[19]};
|
|
||||||
28'hc000050: HREADPLIC <= {{(`XLEN-3){1'b0}},intPriority[20]};
|
|
||||||
28'hc000054: HREADPLIC <= {{(`XLEN-3){1'b0}},intPriority[21]};
|
|
||||||
28'hc000058: HREADPLIC <= {{(`XLEN-3){1'b0}},intPriority[22]};
|
|
||||||
28'hc00005c: HREADPLIC <= {{(`XLEN-3){1'b0}},intPriority[23]};
|
|
||||||
28'hc000060: HREADPLIC <= {{(`XLEN-3){1'b0}},intPriority[24]};
|
|
||||||
28'hc000064: HREADPLIC <= {{(`XLEN-3){1'b0}},intPriority[25]};
|
|
||||||
28'hc000068: HREADPLIC <= {{(`XLEN-3){1'b0}},intPriority[26]};
|
|
||||||
28'hc00006c: HREADPLIC <= {{(`XLEN-3){1'b0}},intPriority[27]};
|
|
||||||
28'hc000070: HREADPLIC <= {{(`XLEN-3){1'b0}},intPriority[28]};
|
|
||||||
28'hc000074: HREADPLIC <= {{(`XLEN-3){1'b0}},intPriority[29]};
|
|
||||||
28'hc000078: HREADPLIC <= {{(`XLEN-3){1'b0}},intPriority[30]};
|
|
||||||
28'hc00007c: HREADPLIC <= {{(`XLEN-3){1'b0}},intPriority[31]};
|
|
||||||
28'hc000080: HREADPLIC <= {{(`XLEN-3){1'b0}},intPriority[32]};
|
|
||||||
28'hc000084: HREADPLIC <= {{(`XLEN-3){1'b0}},intPriority[33]};
|
|
||||||
28'hc000088: HREADPLIC <= {{(`XLEN-3){1'b0}},intPriority[34]};
|
|
||||||
28'hc00008c: HREADPLIC <= {{(`XLEN-3){1'b0}},intPriority[35]};
|
|
||||||
28'hc000090: HREADPLIC <= {{(`XLEN-3){1'b0}},intPriority[36]};
|
|
||||||
28'hc000094: HREADPLIC <= {{(`XLEN-3){1'b0}},intPriority[37]};
|
|
||||||
28'hc000098: HREADPLIC <= {{(`XLEN-3){1'b0}},intPriority[38]};
|
|
||||||
28'hc00009c: HREADPLIC <= {{(`XLEN-3){1'b0}},intPriority[39]};
|
|
||||||
28'hc0000a0: HREADPLIC <= {{(`XLEN-3){1'b0}},intPriority[40]};
|
|
||||||
28'hc0000a4: HREADPLIC <= {{(`XLEN-3){1'b0}},intPriority[41]};
|
|
||||||
28'hc0000a8: HREADPLIC <= {{(`XLEN-3){1'b0}},intPriority[42]};
|
|
||||||
28'hc0000ac: HREADPLIC <= {{(`XLEN-3){1'b0}},intPriority[43]};
|
|
||||||
28'hc0000b0: HREADPLIC <= {{(`XLEN-3){1'b0}},intPriority[44]};
|
|
||||||
28'hc0000b4: HREADPLIC <= {{(`XLEN-3){1'b0}},intPriority[45]};
|
|
||||||
28'hc0000b8: HREADPLIC <= {{(`XLEN-3){1'b0}},intPriority[46]};
|
|
||||||
28'hc0000bc: HREADPLIC <= {{(`XLEN-3){1'b0}},intPriority[47]};
|
|
||||||
28'hc0000c0: HREADPLIC <= {{(`XLEN-3){1'b0}},intPriority[48]};
|
|
||||||
28'hc0000c4: HREADPLIC <= {{(`XLEN-3){1'b0}},intPriority[49]};
|
|
||||||
28'hc0000c8: HREADPLIC <= {{(`XLEN-3){1'b0}},intPriority[50]};
|
|
||||||
28'hc0000cc: HREADPLIC <= {{(`XLEN-3){1'b0}},intPriority[51]};
|
|
||||||
28'hc0000d0: HREADPLIC <= {{(`XLEN-3){1'b0}},intPriority[52]};
|
|
||||||
28'hc0000d4: HREADPLIC <= {{(`XLEN-3){1'b0}},intPriority[53]};
|
|
||||||
// hart 0 configurations
|
|
||||||
28'hc001000: HREADPLIC <= {{(`XLEN-32){1'b0}},intPending[31:1],1'b0};
|
|
||||||
28'hc001004: HREADPLIC <= {{(`XLEN-22){1'b0}},intPending[53:32]};
|
|
||||||
28'hc002000: HREADPLIC <= {{(`XLEN-32){1'b0}},intEn[31:1],1'b0};
|
|
||||||
28'hc002004: HREADPLIC <= {{(`XLEN-22){1'b0}},intEn[53:32]};
|
|
||||||
28'hc200000: HREADPLIC <= {{(`XLEN-3){1'b0}},intThreshold[2:0]};
|
|
||||||
28'hc200004: HREADPLIC <= {{(`XLEN-32){1'b0}},intClaim[31:0]};
|
|
||||||
default: HREADPLIC <= 0;
|
|
||||||
endcase
|
|
||||||
// writing
|
|
||||||
case(entry)
|
|
||||||
// priority assignments
|
|
||||||
28'hc000004: if (memwrite) intPriority[1] <= HWDATA[2:0];
|
|
||||||
28'hc000008: if (memwrite) intPriority[2] <= HWDATA[2:0];
|
|
||||||
28'hc00000c: if (memwrite) intPriority[3] <= HWDATA[2:0];
|
|
||||||
28'hc000010: if (memwrite) intPriority[4] <= HWDATA[2:0];
|
|
||||||
28'hc000014: if (memwrite) intPriority[5] <= HWDATA[2:0];
|
|
||||||
28'hc000018: if (memwrite) intPriority[6] <= HWDATA[2:0];
|
|
||||||
28'hc00001c: if (memwrite) intPriority[7] <= HWDATA[2:0];
|
|
||||||
28'hc000020: if (memwrite) intPriority[8] <= HWDATA[2:0];
|
|
||||||
28'hc000024: if (memwrite) intPriority[9] <= HWDATA[2:0];
|
|
||||||
28'hc000028: if (memwrite) intPriority[10] <= HWDATA[2:0];
|
|
||||||
28'hc00002c: if (memwrite) intPriority[11] <= HWDATA[2:0];
|
|
||||||
28'hc000030: if (memwrite) intPriority[12] <= HWDATA[2:0];
|
|
||||||
28'hc000034: if (memwrite) intPriority[13] <= HWDATA[2:0];
|
|
||||||
28'hc000038: if (memwrite) intPriority[14] <= HWDATA[2:0];
|
|
||||||
28'hc00003c: if (memwrite) intPriority[15] <= HWDATA[2:0];
|
|
||||||
28'hc000040: if (memwrite) intPriority[16] <= HWDATA[2:0];
|
|
||||||
28'hc000044: if (memwrite) intPriority[17] <= HWDATA[2:0];
|
|
||||||
28'hc000048: if (memwrite) intPriority[18] <= HWDATA[2:0];
|
|
||||||
28'hc00004c: if (memwrite) intPriority[19] <= HWDATA[2:0];
|
|
||||||
28'hc000050: if (memwrite) intPriority[20] <= HWDATA[2:0];
|
|
||||||
28'hc000054: if (memwrite) intPriority[21] <= HWDATA[2:0];
|
|
||||||
28'hc000058: if (memwrite) intPriority[22] <= HWDATA[2:0];
|
|
||||||
28'hc00005c: if (memwrite) intPriority[23] <= HWDATA[2:0];
|
|
||||||
28'hc000060: if (memwrite) intPriority[24] <= HWDATA[2:0];
|
|
||||||
28'hc000064: if (memwrite) intPriority[25] <= HWDATA[2:0];
|
|
||||||
28'hc000068: if (memwrite) intPriority[26] <= HWDATA[2:0];
|
|
||||||
28'hc00006c: if (memwrite) intPriority[27] <= HWDATA[2:0];
|
|
||||||
28'hc000070: if (memwrite) intPriority[28] <= HWDATA[2:0];
|
|
||||||
28'hc000074: if (memwrite) intPriority[29] <= HWDATA[2:0];
|
|
||||||
28'hc000078: if (memwrite) intPriority[30] <= HWDATA[2:0];
|
|
||||||
28'hc00007c: if (memwrite) intPriority[31] <= HWDATA[2:0];
|
|
||||||
28'hc000080: if (memwrite) intPriority[32] <= HWDATA[2:0];
|
|
||||||
28'hc000084: if (memwrite) intPriority[33] <= HWDATA[2:0];
|
|
||||||
28'hc000088: if (memwrite) intPriority[34] <= HWDATA[2:0];
|
|
||||||
28'hc00008c: if (memwrite) intPriority[35] <= HWDATA[2:0];
|
|
||||||
28'hc000090: if (memwrite) intPriority[36] <= HWDATA[2:0];
|
|
||||||
28'hc000094: if (memwrite) intPriority[37] <= HWDATA[2:0];
|
|
||||||
28'hc000098: if (memwrite) intPriority[38] <= HWDATA[2:0];
|
|
||||||
28'hc00009c: if (memwrite) intPriority[39] <= HWDATA[2:0];
|
|
||||||
28'hc0000a0: if (memwrite) intPriority[40] <= HWDATA[2:0];
|
|
||||||
28'hc0000a4: if (memwrite) intPriority[41] <= HWDATA[2:0];
|
|
||||||
28'hc0000a8: if (memwrite) intPriority[42] <= HWDATA[2:0];
|
|
||||||
28'hc0000ac: if (memwrite) intPriority[43] <= HWDATA[2:0];
|
|
||||||
28'hc0000b0: if (memwrite) intPriority[44] <= HWDATA[2:0];
|
|
||||||
28'hc0000b4: if (memwrite) intPriority[45] <= HWDATA[2:0];
|
|
||||||
28'hc0000b8: if (memwrite) intPriority[46] <= HWDATA[2:0];
|
|
||||||
28'hc0000bc: if (memwrite) intPriority[47] <= HWDATA[2:0];
|
|
||||||
28'hc0000c0: if (memwrite) intPriority[48] <= HWDATA[2:0];
|
|
||||||
28'hc0000c4: if (memwrite) intPriority[49] <= HWDATA[2:0];
|
|
||||||
28'hc0000c8: if (memwrite) intPriority[50] <= HWDATA[2:0];
|
|
||||||
28'hc0000cc: if (memwrite) intPriority[51] <= HWDATA[2:0];
|
|
||||||
28'hc0000d0: if (memwrite) intPriority[52] <= HWDATA[2:0];
|
|
||||||
28'hc0000d4: if (memwrite) intPriority[53] <= HWDATA[2:0];
|
|
||||||
// hart 0 configurations
|
|
||||||
28'hc002000: if (memwrite) intEn[31:1] <= HWDATA[31:1];
|
|
||||||
28'hc002004: if (memwrite) intEn[53:32] <= HWDATA[22:0];
|
|
||||||
endcase
|
|
||||||
end
|
|
||||||
end else begin // 32-bit
|
|
||||||
always @(posedge HCLK) begin
|
|
||||||
// reading
|
|
||||||
case(entry)
|
|
||||||
// priority assignments
|
|
||||||
28'hc000004: HREADPLIC <= {{(`XLEN-3){1'b0}},intPriority[1]};
|
|
||||||
28'hc000008: HREADPLIC <= {{(`XLEN-3){1'b0}},intPriority[2]};
|
|
||||||
28'hc00000c: HREADPLIC <= {{(`XLEN-3){1'b0}},intPriority[3]};
|
|
||||||
28'hc000010: HREADPLIC <= {{(`XLEN-3){1'b0}},intPriority[4]};
|
|
||||||
28'hc000014: HREADPLIC <= {{(`XLEN-3){1'b0}},intPriority[5]};
|
|
||||||
28'hc000018: HREADPLIC <= {{(`XLEN-3){1'b0}},intPriority[6]};
|
|
||||||
28'hc00001c: HREADPLIC <= {{(`XLEN-3){1'b0}},intPriority[7]};
|
|
||||||
28'hc000020: HREADPLIC <= {{(`XLEN-3){1'b0}},intPriority[8]};
|
|
||||||
28'hc000024: HREADPLIC <= {{(`XLEN-3){1'b0}},intPriority[9]};
|
|
||||||
28'hc000028: HREADPLIC <= {{(`XLEN-3){1'b0}},intPriority[10]};
|
|
||||||
28'hc00002c: HREADPLIC <= {{(`XLEN-3){1'b0}},intPriority[11]};
|
|
||||||
28'hc000030: HREADPLIC <= {{(`XLEN-3){1'b0}},intPriority[12]};
|
|
||||||
28'hc000034: HREADPLIC <= {{(`XLEN-3){1'b0}},intPriority[13]};
|
|
||||||
28'hc000038: HREADPLIC <= {{(`XLEN-3){1'b0}},intPriority[14]};
|
|
||||||
28'hc00003c: HREADPLIC <= {{(`XLEN-3){1'b0}},intPriority[15]};
|
|
||||||
28'hc000040: HREADPLIC <= {{(`XLEN-3){1'b0}},intPriority[16]};
|
|
||||||
28'hc000044: HREADPLIC <= {{(`XLEN-3){1'b0}},intPriority[17]};
|
|
||||||
28'hc000048: HREADPLIC <= {{(`XLEN-3){1'b0}},intPriority[18]};
|
|
||||||
28'hc00004c: HREADPLIC <= {{(`XLEN-3){1'b0}},intPriority[19]};
|
|
||||||
28'hc000050: HREADPLIC <= {{(`XLEN-3){1'b0}},intPriority[20]};
|
|
||||||
28'hc000054: HREADPLIC <= {{(`XLEN-3){1'b0}},intPriority[21]};
|
|
||||||
28'hc000058: HREADPLIC <= {{(`XLEN-3){1'b0}},intPriority[22]};
|
|
||||||
28'hc00005c: HREADPLIC <= {{(`XLEN-3){1'b0}},intPriority[23]};
|
|
||||||
28'hc000060: HREADPLIC <= {{(`XLEN-3){1'b0}},intPriority[24]};
|
|
||||||
28'hc000064: HREADPLIC <= {{(`XLEN-3){1'b0}},intPriority[25]};
|
|
||||||
28'hc000068: HREADPLIC <= {{(`XLEN-3){1'b0}},intPriority[26]};
|
|
||||||
28'hc00006c: HREADPLIC <= {{(`XLEN-3){1'b0}},intPriority[27]};
|
|
||||||
28'hc000070: HREADPLIC <= {{(`XLEN-3){1'b0}},intPriority[28]};
|
|
||||||
28'hc000074: HREADPLIC <= {{(`XLEN-3){1'b0}},intPriority[29]};
|
|
||||||
28'hc000078: HREADPLIC <= {{(`XLEN-3){1'b0}},intPriority[30]};
|
|
||||||
28'hc00007c: HREADPLIC <= {{(`XLEN-3){1'b0}},intPriority[31]};
|
|
||||||
28'hc000080: HREADPLIC <= {{(`XLEN-3){1'b0}},intPriority[32]};
|
|
||||||
28'hc000084: HREADPLIC <= {{(`XLEN-3){1'b0}},intPriority[33]};
|
|
||||||
28'hc000088: HREADPLIC <= {{(`XLEN-3){1'b0}},intPriority[34]};
|
|
||||||
28'hc00008c: HREADPLIC <= {{(`XLEN-3){1'b0}},intPriority[35]};
|
|
||||||
28'hc000090: HREADPLIC <= {{(`XLEN-3){1'b0}},intPriority[36]};
|
|
||||||
28'hc000094: HREADPLIC <= {{(`XLEN-3){1'b0}},intPriority[37]};
|
|
||||||
28'hc000098: HREADPLIC <= {{(`XLEN-3){1'b0}},intPriority[38]};
|
|
||||||
28'hc00009c: HREADPLIC <= {{(`XLEN-3){1'b0}},intPriority[39]};
|
|
||||||
28'hc0000a0: HREADPLIC <= {{(`XLEN-3){1'b0}},intPriority[40]};
|
|
||||||
28'hc0000a4: HREADPLIC <= {{(`XLEN-3){1'b0}},intPriority[41]};
|
|
||||||
28'hc0000a8: HREADPLIC <= {{(`XLEN-3){1'b0}},intPriority[42]};
|
|
||||||
28'hc0000ac: HREADPLIC <= {{(`XLEN-3){1'b0}},intPriority[43]};
|
|
||||||
28'hc0000b0: HREADPLIC <= {{(`XLEN-3){1'b0}},intPriority[44]};
|
|
||||||
28'hc0000b4: HREADPLIC <= {{(`XLEN-3){1'b0}},intPriority[45]};
|
|
||||||
28'hc0000b8: HREADPLIC <= {{(`XLEN-3){1'b0}},intPriority[46]};
|
|
||||||
28'hc0000bc: HREADPLIC <= {{(`XLEN-3){1'b0}},intPriority[47]};
|
|
||||||
28'hc0000c0: HREADPLIC <= {{(`XLEN-3){1'b0}},intPriority[48]};
|
|
||||||
28'hc0000c4: HREADPLIC <= {{(`XLEN-3){1'b0}},intPriority[49]};
|
|
||||||
28'hc0000c8: HREADPLIC <= {{(`XLEN-3){1'b0}},intPriority[50]};
|
|
||||||
28'hc0000cc: HREADPLIC <= {{(`XLEN-3){1'b0}},intPriority[51]};
|
|
||||||
28'hc0000d0: HREADPLIC <= {{(`XLEN-3){1'b0}},intPriority[52]};
|
|
||||||
28'hc0000d4: HREADPLIC <= {{(`XLEN-3){1'b0}},intPriority[53]};
|
|
||||||
// hart 0 configurations
|
|
||||||
28'hc001000: HREADPLIC <= {{(`XLEN-32){1'b0}},intPending[31:1],1'b0};
|
|
||||||
28'hc001004: HREADPLIC <= {{(`XLEN-22){1'b0}},intPending[53:32]};
|
|
||||||
28'hc002000: HREADPLIC <= {{(`XLEN-32){1'b0}},intEn[31:1],1'b0};
|
|
||||||
28'hc002004: HREADPLIC <= {{(`XLEN-22){1'b0}},intEn[53:32]};
|
|
||||||
28'hc200000: HREADPLIC <= {{(`XLEN-3){1'b0}},intThreshold[2:0]};
|
|
||||||
28'hc200004: HREADPLIC <= {{(`XLEN-32){1'b0}},intClaim[31:0]};
|
|
||||||
default: HREADPLIC <= 0;
|
|
||||||
endcase
|
|
||||||
// writing
|
|
||||||
case(entry)
|
|
||||||
// priority assignments
|
|
||||||
28'hc000004: if (memwrite) intPriority[1] <= HWDATA[2:0];
|
|
||||||
28'hc000008: if (memwrite) intPriority[2] <= HWDATA[2:0];
|
|
||||||
28'hc00000c: if (memwrite) intPriority[3] <= HWDATA[2:0];
|
|
||||||
28'hc000010: if (memwrite) intPriority[4] <= HWDATA[2:0];
|
|
||||||
28'hc000014: if (memwrite) intPriority[5] <= HWDATA[2:0];
|
|
||||||
28'hc000018: if (memwrite) intPriority[6] <= HWDATA[2:0];
|
|
||||||
28'hc00001c: if (memwrite) intPriority[7] <= HWDATA[2:0];
|
|
||||||
28'hc000020: if (memwrite) intPriority[8] <= HWDATA[2:0];
|
|
||||||
28'hc000024: if (memwrite) intPriority[9] <= HWDATA[2:0];
|
|
||||||
28'hc000028: if (memwrite) intPriority[10] <= HWDATA[2:0];
|
|
||||||
28'hc00002c: if (memwrite) intPriority[11] <= HWDATA[2:0];
|
|
||||||
28'hc000030: if (memwrite) intPriority[12] <= HWDATA[2:0];
|
|
||||||
28'hc000034: if (memwrite) intPriority[13] <= HWDATA[2:0];
|
|
||||||
28'hc000038: if (memwrite) intPriority[14] <= HWDATA[2:0];
|
|
||||||
28'hc00003c: if (memwrite) intPriority[15] <= HWDATA[2:0];
|
|
||||||
28'hc000040: if (memwrite) intPriority[16] <= HWDATA[2:0];
|
|
||||||
28'hc000044: if (memwrite) intPriority[17] <= HWDATA[2:0];
|
|
||||||
28'hc000048: if (memwrite) intPriority[18] <= HWDATA[2:0];
|
|
||||||
28'hc00004c: if (memwrite) intPriority[19] <= HWDATA[2:0];
|
|
||||||
28'hc000050: if (memwrite) intPriority[20] <= HWDATA[2:0];
|
|
||||||
28'hc000054: if (memwrite) intPriority[21] <= HWDATA[2:0];
|
|
||||||
28'hc000058: if (memwrite) intPriority[22] <= HWDATA[2:0];
|
|
||||||
28'hc00005c: if (memwrite) intPriority[23] <= HWDATA[2:0];
|
|
||||||
28'hc000060: if (memwrite) intPriority[24] <= HWDATA[2:0];
|
|
||||||
28'hc000064: if (memwrite) intPriority[25] <= HWDATA[2:0];
|
|
||||||
28'hc000068: if (memwrite) intPriority[26] <= HWDATA[2:0];
|
|
||||||
28'hc00006c: if (memwrite) intPriority[27] <= HWDATA[2:0];
|
|
||||||
28'hc000070: if (memwrite) intPriority[28] <= HWDATA[2:0];
|
|
||||||
28'hc000074: if (memwrite) intPriority[29] <= HWDATA[2:0];
|
|
||||||
28'hc000078: if (memwrite) intPriority[30] <= HWDATA[2:0];
|
|
||||||
28'hc00007c: if (memwrite) intPriority[31] <= HWDATA[2:0];
|
|
||||||
28'hc000080: if (memwrite) intPriority[32] <= HWDATA[2:0];
|
|
||||||
28'hc000084: if (memwrite) intPriority[33] <= HWDATA[2:0];
|
|
||||||
28'hc000088: if (memwrite) intPriority[34] <= HWDATA[2:0];
|
|
||||||
28'hc00008c: if (memwrite) intPriority[35] <= HWDATA[2:0];
|
|
||||||
28'hc000090: if (memwrite) intPriority[36] <= HWDATA[2:0];
|
|
||||||
28'hc000094: if (memwrite) intPriority[37] <= HWDATA[2:0];
|
|
||||||
28'hc000098: if (memwrite) intPriority[38] <= HWDATA[2:0];
|
|
||||||
28'hc00009c: if (memwrite) intPriority[39] <= HWDATA[2:0];
|
|
||||||
28'hc0000a0: if (memwrite) intPriority[40] <= HWDATA[2:0];
|
|
||||||
28'hc0000a4: if (memwrite) intPriority[41] <= HWDATA[2:0];
|
|
||||||
28'hc0000a8: if (memwrite) intPriority[42] <= HWDATA[2:0];
|
|
||||||
28'hc0000ac: if (memwrite) intPriority[43] <= HWDATA[2:0];
|
|
||||||
28'hc0000b0: if (memwrite) intPriority[44] <= HWDATA[2:0];
|
|
||||||
28'hc0000b4: if (memwrite) intPriority[45] <= HWDATA[2:0];
|
|
||||||
28'hc0000b8: if (memwrite) intPriority[46] <= HWDATA[2:0];
|
|
||||||
28'hc0000bc: if (memwrite) intPriority[47] <= HWDATA[2:0];
|
|
||||||
28'hc0000c0: if (memwrite) intPriority[48] <= HWDATA[2:0];
|
|
||||||
28'hc0000c4: if (memwrite) intPriority[49] <= HWDATA[2:0];
|
|
||||||
28'hc0000c8: if (memwrite) intPriority[50] <= HWDATA[2:0];
|
|
||||||
28'hc0000cc: if (memwrite) intPriority[51] <= HWDATA[2:0];
|
|
||||||
28'hc0000d0: if (memwrite) intPriority[52] <= HWDATA[2:0];
|
|
||||||
28'hc0000d4: if (memwrite) intPriority[53] <= HWDATA[2:0];
|
|
||||||
// hart 0 configurations
|
|
||||||
28'hc002000: if (memwrite) intEn[31:1] <= HWDATA[31:1];
|
|
||||||
28'hc002004: if (memwrite) intEn[53:32] <= HWDATA[22:0];
|
|
||||||
endcase
|
|
||||||
end
|
|
||||||
end
|
|
||||||
endgenerate
|
|
||||||
|
|
||||||
endmodule
|
|
||||||
|
|
||||||
@ -49,7 +49,7 @@ module uartPC16550D(
|
|||||||
output logic SOUT, RTSb, DTRb, OUT1b, OUT2b
|
output logic SOUT, RTSb, DTRb, OUT1b, OUT2b
|
||||||
);
|
);
|
||||||
|
|
||||||
// transmit and receive states
|
// transmit and receive states // *** neeed to work on synth warning -- it wants to make enums 32 bits by default
|
||||||
typedef enum {UART_IDLE, UART_ACTIVE, UART_DONE, UART_BREAK} statetype;
|
typedef enum {UART_IDLE, UART_ACTIVE, UART_DONE, UART_BREAK} statetype;
|
||||||
|
|
||||||
// Registers
|
// Registers
|
||||||
|
|||||||
@ -67,7 +67,7 @@ module uncore (
|
|||||||
logic [`XLEN-1:0] HREADBootTim;
|
logic [`XLEN-1:0] HREADBootTim;
|
||||||
logic HSELBootTim, HSELBootTimD, HRESPBootTim, HREADYBootTim;
|
logic HSELBootTim, HSELBootTimD, HRESPBootTim, HREADYBootTim;
|
||||||
logic [1:0] MemRWboottim;
|
logic [1:0] MemRWboottim;
|
||||||
logic UARTIntr;// *** will need to tie INTR to an interrupt handler
|
logic UARTIntr,GPIOIntr;
|
||||||
|
|
||||||
|
|
||||||
// AHB Address decoder
|
// AHB Address decoder
|
||||||
|
|||||||
@ -356,7 +356,7 @@ module testbench();
|
|||||||
};
|
};
|
||||||
|
|
||||||
string tests32periph[] = '{
|
string tests32periph[] = '{
|
||||||
"rv32i-periph/WALLY-PLIC", "2000"
|
"rv32i-periph/WALLY-PLIC", "2080"
|
||||||
};
|
};
|
||||||
|
|
||||||
|
|
||||||
|
|||||||
Loading…
Reference in New Issue
Block a user