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Removed ignore request from busfsm.

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This commit is contained in:
Ross Thompson 2022-08-28 21:12:27 -05:00
parent dd00474956
commit 35d0b759d1
3 changed files with 11 additions and 13 deletions
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2
pipelined/src/ifu/ifu.sv
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@ -249,7 +249,7 @@ module ifu (
flopen #(`XLEN) fb(.clk, .en(IFUBusRead), .d(HRDATA), .q(AllInstrRawF[31:0])); flopen #(`XLEN) fb(.clk, .en(IFUBusRead), .d(HRDATA), .q(AllInstrRawF[31:0]));
busfsm #(LOGBWPL) busfsm( busfsm #(LOGBWPL) busfsm(
.clk, .reset, .IgnoreRequest(ITLBMissF), .RW(NonIROMMemRWM), .clk, .reset, .RW(NonIROMMemRWM & ~{ITLBMissF, ITLBMissF}),
.BusAck(IFUBusAck), .BusInit(IFUBusInit), .CPUBusy, .BusAck(IFUBusAck), .BusInit(IFUBusInit), .CPUBusy,
.BusStall, .BusWrite(), .BusRead(IFUBusRead), .BusStall, .BusWrite(), .BusRead(IFUBusRead),
.HTRANS(IFUHTRANS), .BusCommitted()); .HTRANS(IFUHTRANS), .BusCommitted());

20
pipelined/src/lsu/busfsm.sv
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@ -35,7 +35,6 @@ module busfsm #(parameter integer LOGWPL)
(input logic clk, (input logic clk,
input logic reset, input logic reset,
input logic IgnoreRequest,
input logic [1:0] RW, input logic [1:0] RW,
input logic BusAck, input logic BusAck,
input logic BusInit, // This might be better as LSUBusLock, or to send this using BusAck. input logic BusInit, // This might be better as LSUBusLock, or to send this using BusAck.
@ -65,30 +64,29 @@ module busfsm #(parameter integer LOGWPL)
always_comb begin always_comb begin
case(BusCurrState) case(BusCurrState)
STATE_BUS_READY: if(IgnoreRequest) BusNextState = STATE_BUS_READY; STATE_BUS_READY: if(RW[0]) BusNextState = STATE_BUS_UNCACHED_WRITE;
else if(RW[0]) BusNextState = STATE_BUS_UNCACHED_WRITE; else if(RW[1]) BusNextState = STATE_BUS_UNCACHED_READ;
else if(RW[1]) BusNextState = STATE_BUS_UNCACHED_READ;
else BusNextState = STATE_BUS_READY; else BusNextState = STATE_BUS_READY;
STATE_BUS_UNCACHED_WRITE: if(BusAck) BusNextState = STATE_BUS_UNCACHED_WRITE_DONE; STATE_BUS_UNCACHED_WRITE: if(BusAck) BusNextState = STATE_BUS_UNCACHED_WRITE_DONE;
else BusNextState = STATE_BUS_UNCACHED_WRITE; else BusNextState = STATE_BUS_UNCACHED_WRITE;
STATE_BUS_UNCACHED_READ: if(BusAck) BusNextState = STATE_BUS_UNCACHED_READ_DONE; STATE_BUS_UNCACHED_READ: if(BusAck) BusNextState = STATE_BUS_UNCACHED_READ_DONE;
else BusNextState = STATE_BUS_UNCACHED_READ; else BusNextState = STATE_BUS_UNCACHED_READ;
STATE_BUS_UNCACHED_WRITE_DONE: if(CPUBusy) BusNextState = STATE_BUS_CPU_BUSY; STATE_BUS_UNCACHED_WRITE_DONE: if(CPUBusy) BusNextState = STATE_BUS_CPU_BUSY;
else BusNextState = STATE_BUS_READY; else BusNextState = STATE_BUS_READY;
STATE_BUS_UNCACHED_READ_DONE: if(CPUBusy) BusNextState = STATE_BUS_CPU_BUSY; STATE_BUS_UNCACHED_READ_DONE: if(CPUBusy) BusNextState = STATE_BUS_CPU_BUSY;
else BusNextState = STATE_BUS_READY; else BusNextState = STATE_BUS_READY;
STATE_BUS_CPU_BUSY: if(CPUBusy) BusNextState = STATE_BUS_CPU_BUSY; STATE_BUS_CPU_BUSY: if(CPUBusy) BusNextState = STATE_BUS_CPU_BUSY;
else BusNextState = STATE_BUS_READY; else BusNextState = STATE_BUS_READY;
default: BusNextState = STATE_BUS_READY; default: BusNextState = STATE_BUS_READY;
endcase endcase
end end
assign BusStall = (BusCurrState == STATE_BUS_READY & ~IgnoreRequest & |RW) | assign BusStall = (BusCurrState == STATE_BUS_READY & |RW) |
(BusCurrState == STATE_BUS_UNCACHED_WRITE) | (BusCurrState == STATE_BUS_UNCACHED_WRITE) |
(BusCurrState == STATE_BUS_UNCACHED_READ); (BusCurrState == STATE_BUS_UNCACHED_READ);
assign BusWrite = (BusCurrState == STATE_BUS_READY & RW[0] & ~IgnoreRequest) | assign BusWrite = (BusCurrState == STATE_BUS_READY & RW[0]) |
(BusCurrState == STATE_BUS_UNCACHED_WRITE); (BusCurrState == STATE_BUS_UNCACHED_WRITE);
assign BusRead = (BusCurrState == STATE_BUS_READY & RW[1] & ~IgnoreRequest) | assign BusRead = (BusCurrState == STATE_BUS_READY & RW[1]) |
(BusCurrState == STATE_BUS_UNCACHED_READ); (BusCurrState == STATE_BUS_UNCACHED_READ);
assign BusCommitted = BusCurrState != STATE_BUS_READY; assign BusCommitted = BusCurrState != STATE_BUS_READY;

2
pipelined/src/lsu/lsu.sv
View File

@ -269,7 +269,7 @@ module lsu (
assign LSUHWDATA = LSUWriteDataM[`XLEN-1:0]; assign LSUHWDATA = LSUWriteDataM[`XLEN-1:0];
busfsm #(LOGBWPL) busfsm( busfsm #(LOGBWPL) busfsm(
.clk, .reset, .IgnoreRequest, .RW(LSURWM), .clk, .reset, .RW(LSURWM & ~{IgnoreRequest, IgnoreRequest}),
.BusAck(LSUBusAck), .BusInit(LSUBusInit), .CPUBusy, .BusAck(LSUBusAck), .BusInit(LSUBusInit), .CPUBusy,
.BusStall, .BusWrite(LSUBusWrite), .BusRead(LSUBusRead), .BusStall, .BusWrite(LSUBusWrite), .BusRead(LSUBusRead),
.HTRANS(LSUHTRANS), .BusCommitted(BusCommittedM)); .HTRANS(LSUHTRANS), .BusCommitted(BusCommittedM));