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Cleanup multimanager.

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This commit is contained in:
Ross Thompson 2022-08-31 12:04:44 -05:00
parent 1e752c1268
commit 352f7443c2
1 changed files with 13 additions and 19 deletions
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24
pipelined/src/ebu/ahbmultimanager.sv
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@ -79,7 +79,6 @@ module ahbmultimanager
logic [1:0] save, restore, dis, sel; logic [1:0] save, restore, dis, sel;
logic both; logic both;
logic DoArbitration;
logic [`PA_BITS-1:0] IFUHADDRSave, IFUHADDRRestore; logic [`PA_BITS-1:0] IFUHADDRSave, IFUHADDRRestore;
logic [1:0] IFUHTRANSSave, IFUHTRANSRestore; logic [1:0] IFUHTRANSSave, IFUHTRANSRestore;
@ -145,25 +144,24 @@ module ahbmultimanager
assign HMASTLOCK = 0; // no locking supported assign HMASTLOCK = 0; // no locking supported
assign HWRITE = sel[1] ? LSUHWRITERestore : sel[0] ? 1'b0 : '0; assign HWRITE = sel[1] ? LSUHWRITERestore : sel[0] ? 1'b0 : '0;
// data phase muxing
assign HWDATA = LSUHWDATA;
assign HWSTRB = LSUHWSTRB;
// HRDATA is sent to all managers at the core level.
// basic arb always selects LSU when both // basic arb always selects LSU when both
// Manager 0 (IFU)
assign save[0] = CurrState == IDLE & both; assign save[0] = CurrState == IDLE & both;
assign restore[0] = CurrState == ARBITRATE; assign restore[0] = CurrState == ARBITRATE;
assign dis[0] = CurrState == ARBITRATE; assign dis[0] = CurrState == ARBITRATE;
assign sel[0] = (NextState == ARBITRATE) ? 1'b0 : IFUReq; assign sel[0] = (NextState == ARBITRATE) ? 1'b0 : IFUReq;
// Manager 1 (LSU)
//
assign save[1] = 1'b0; assign save[1] = 1'b0;
assign restore[1] = 1'b0; assign restore[1] = 1'b0;
assign dis[1] = 1'b0; assign dis[1] = 1'b0;
assign sel[1] = NextState == ARBITRATE ? 1'b1: LSUReq; assign sel[1] = NextState == ARBITRATE ? 1'b1: LSUReq;
// Bus State FSM // Bus State FSM
// Data accesses have priority over instructions. However, if a data access comes
// while an cache line read is occuring, the line read finishes before
// the data access can take place.
flopenl #(.TYPE(statetype)) busreg(HCLK, ~HRESETn, 1'b1, NextState, IDLE, CurrState); flopenl #(.TYPE(statetype)) busreg(HCLK, ~HRESETn, 1'b1, NextState, IDLE, CurrState);
always_comb always_comb
case (CurrState) case (CurrState)
@ -172,13 +170,9 @@ module ahbmultimanager
ARBITRATE: if (HREADY & WordCountFlag) NextState = IDLE; ARBITRATE: if (HREADY & WordCountFlag) NextState = IDLE;
else NextState = ARBITRATE; else NextState = ARBITRATE;
default: NextState = IDLE; default: NextState = IDLE;
endcase // case (CurrState) endcase
assign DoArbitration = CurrState == ARBITRATE;
assign HWDATA = LSUHWDATA;
assign HWSTRB = LSUHWSTRB;
// Manager needs to count beats.
flopenr #(4) flopenr #(4)
WordCountReg(.clk(HCLK), WordCountReg(.clk(HCLK),
.reset(~HRESETn | CntReset), .reset(~HRESETn | CntReset),