forked from Github_Repos/cvw
fixed some fpu lint errors
This commit is contained in:
Katherine Parry
parent
6c4aa624a5
commit
30ac22edff
215
wally-pipelined/fpu-testfloat/FMA/tbgen/tb.sv
Normal file
215
wally-pipelined/fpu-testfloat/FMA/tbgen/tb.sv
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`include "../../../config/rv64icfd/wally-config.vh"
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module testbench3();
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logic [31:0] errors=0;
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logic [31:0] vectornum=0;
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logic [`FLEN*4+7:0] testvectors[6133248:0];
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// logic [63:0] X,Y,Z;
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logic [`FLEN-1:0] ans;
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logic [7:0] flags;
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logic [2:0] FrmE;
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logic FmtE;
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logic [`FLEN-1:0] FMAResM;
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logic [4:0] FMAFlgM;
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integer fp;
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logic [2:0] FOpCtrlE;
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logic [2*`NF+1:0] ProdManE;
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logic [3*`NF+5:0] AlignedAddendE;
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logic [`NE+1:0] ProdExpE;
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logic AddendStickyE;
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logic KillProdE;
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// logic XZeroE;
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// logic YZeroE;
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// logic ZZeroE;
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// logic XDenormE;
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// logic YDenormE;
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// logic ZDenormE;
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// logic XInfE;
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// logic YInfE;
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// logic ZInfE;
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// logic XNaNE;
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// logic YNaNE;
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// logic ZNaNE;
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logic wnan;
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// logic XNaNE;
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// logic YNaNE;
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// logic ZNaNE;
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logic ansnan, clk;
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assign FOpCtrlE = 3'b0;
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// nearest even - 000
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// twords zero - 001
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// down - 010
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// up - 011
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// nearest max mag - 100
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assign FrmE = 3'b000;
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assign FmtE = 1'b0;
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logic [`FLEN-1:0] X, Y, Z;
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// logic FmtE;
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// logic [2:0] FOpCtrlE;
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logic XSgnE, YSgnE, ZSgnE;
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logic [`NE-1:0] XExpE, YExpE, ZExpE;
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logic [`NF-1:0] XFracE, YFracE, ZFracE;
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logic XAssumed1E, YAssumed1E, ZAssumed1E;
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logic XNormE;
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logic XNaNE, YNaNE, ZNaNE;
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logic XSNaNE, YSNaNE, ZSNaNE;
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logic XDenormE, YDenormE, ZDenormE;
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logic XZeroE, YZeroE, ZZeroE;
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logic [`NE-1:0] BiasE;
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logic XInfE, YInfE, ZInfE;
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logic XExpMaxE;
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//***rename to make significand = 1.frac m = significand
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logic XFracZero, YFracZero, ZFracZero; // input fraction zero
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logic XExpZero, YExpZero, ZExpZero; // input exponent zero
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logic [`FLEN-1:0] Addend; // value to add (Z or zero)
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logic YExpMaxE, ZExpMaxE; // input exponent all 1s
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assign Addend = FOpCtrlE[2] ? (`FLEN)'(0) : Z; // Z is only used in the FMA, and is set to Zero if a multiply opperation
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assign XSgnE = FmtE ? X[`FLEN-1] : X[31];
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assign YSgnE = FmtE ? Y[`FLEN-1] : Y[31];
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assign ZSgnE = FmtE ? Addend[`FLEN-1] : Addend[31];
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assign XExpE = FmtE ? X[62:52] : {3'b0, X[30:23]};//{X[30], {3{~X[30]&~XExpZero|XExpMaxE}}, X[29:23]};
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assign YExpE = FmtE ? Y[62:52] : {3'b0, Y[30:23]};//{Y[30], {3{~Y[30]&~YExpZero|YExpMaxE}}, Y[29:23]};
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assign ZExpE = FmtE ? Addend[62:52] : {3'b0, Addend[30:23]};//{Addend[30], {3{~Addend[30]&~ZExpZero|ZExpMaxE}}, Addend[29:23]};
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assign XFracE = FmtE ? X[`NF-1:0] : {X[22:0], 29'b0};
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assign YFracE = FmtE ? Y[`NF-1:0] : {Y[22:0], 29'b0};
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assign ZFracE = FmtE ? Addend[`NF-1:0] : {Addend[22:0], 29'b0};
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assign XAssumed1E = FmtE ? |X[62:52] : |X[30:23];
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assign YAssumed1E = FmtE ? |Y[62:52] : |Y[30:23];
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assign ZAssumed1E = FmtE ? |Z[62:52] : |Z[30:23];
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assign XExpZero = ~XAssumed1E;
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assign YExpZero = ~YAssumed1E;
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assign ZExpZero = ~ZAssumed1E;
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assign XFracZero = ~|XFracE;
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assign YFracZero = ~|YFracE;
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assign ZFracZero = ~|ZFracE;
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assign XExpMaxE = FmtE ? &X[62:52] : &X[30:23];
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assign YExpMaxE = FmtE ? &Y[62:52] : &Y[30:23];
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assign ZExpMaxE = FmtE ? &Z[62:52] : &Z[30:23];
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assign XNormE = ~(XExpMaxE|XExpZero);
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assign XNaNE = XExpMaxE & ~XFracZero;
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assign YNaNE = YExpMaxE & ~YFracZero;
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assign ZNaNE = ZExpMaxE & ~ZFracZero;
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assign XSNaNE = XNaNE&~XFracE[`NF-1];
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assign YSNaNE = YNaNE&~YFracE[`NF-1];
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assign ZSNaNE = ZNaNE&~ZFracE[`NF-1];
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assign XDenormE = XExpZero & ~XFracZero;
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assign YDenormE = YExpZero & ~YFracZero;
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assign ZDenormE = ZExpZero & ~ZFracZero;
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assign XInfE = XExpMaxE & XFracZero;
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assign YInfE = YExpMaxE & YFracZero;
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assign ZInfE = ZExpMaxE & ZFracZero;
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assign XZeroE = XExpZero & XFracZero;
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assign YZeroE = YExpZero & YFracZero;
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assign ZZeroE = ZExpZero & ZFracZero;
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assign BiasE = FmtE ? {1'b0, {`NE-1{1'b1}}} : 13'h7f;
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assign wnan = FmtE ? &FMAResM[`FLEN-2:`NF] && |FMAResM[`NF-1:0] : &FMAResM[30:23] && |FMAResM[22:0];
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// assign XNaNE = FmtE ? &X[62:52] && |X[51:0] : &X[62:55] && |X[54:32];
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// assign YNaNE = FmtE ? &Y[62:52] && |Y[51:0] : &Y[62:55] && |Y[54:32];
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// assign ZNaNE = FmtE ? &Z[62:52] && |Z[51:0] : &Z[62:55] && |Z[54:32];
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assign ansnan = FmtE ? &ans[`FLEN-2:`NF] && |ans[`NF-1:0] : &ans[30:23] && |ans[22:0];
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// instantiate device under test
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fma1 UUT1(.XManE({XAssumed1E,XFracE}), .YManE({YAssumed1E,YFracE}), .ZManE({ZAssumed1E,ZFracE}), .*);
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fma2 UUT2(.XSgnM(XSgnE), .YSgnM(YSgnE), .ZSgnM(ZSgnE), .XExpM(XExpE), .YExpM(YExpE), .ZExpM(ZExpE), .XManM({XAssumed1E,XFracE}), .YManM({YAssumed1E,YFracE}), .ZManM({ZAssumed1E,ZFracE}), .XNaNM(XNaNE), .YNaNM(YNaNE), .ZNaNM(ZNaNE), .XZeroM(XZeroE), .YZeroM(YZeroE), .ZZeroM(ZZeroE), .XInfM(XInfE), .YInfM(YInfE), .ZInfM(ZInfE), .XSNaNM(XSNaNE), .YSNaNM(YSNaNE), .ZSNaNM(ZSNaNE),
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// .FSrcXE, .FSrcYE, .FSrcZE, .FSrcXM, .FSrcYM, .FSrcZM,
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.FOpCtrlM(FOpCtrlE[2:0]), .KillProdM(KillProdE), .AddendStickyM(AddendStickyE), .ProdExpM(ProdExpE), .AlignedAddendM(AlignedAddendE), .ProdManM(ProdManE),
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.FmtM(FmtE), .FrmM(FrmE), .FMAFlgM, .FMAResM);
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// generate clock
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always
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begin
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clk = 1; #5; clk = 0; #5;
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end
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// at start of test, load vectors
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// and pulse reset
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initial
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begin
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$readmemh("testFloatNoSpace", testvectors);
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end
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// apply test vectors on rising edge of clk
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always @(posedge clk)
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begin
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#1;
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if (FmtE==1'b1) {X, Y, Z, ans, flags} = testvectors[vectornum];
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else begin X = {{32{1'b1}}, testvectors[vectornum][135:104]};
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Y = {{32{1'b1}}, testvectors[vectornum][103:72]};
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Z = {{32{1'b1}}, testvectors[vectornum][71:40]};
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ans = {{32{1'b1}}, testvectors[vectornum][39:8]};
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flags = testvectors[vectornum][7:0];
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end
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end
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// check results on falling edge of clk
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always @(negedge clk) begin
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// fp = $fopen("/home/kparry/riscv-wally/wally-pipelined/src/fpu/FMA/tbgen/results.dat","w");
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if((FmtE==1'b1) & (FMAFlgM != flags[4:0] || (!wnan && (FMAResM != ans)) || (wnan && ansnan && ~((XNaNE && (FMAResM[`FLEN-2:0] == {XExpE,1'b1,X[`NF-2:0]})) || (YNaNE && (FMAResM[`FLEN-2:0] == {YExpE,1'b1,Y[`NF-2:0]})) || (ZNaNE && (FMAResM[`FLEN-2:0] == {ZExpE,1'b1,Z[`NF-2:0]})) || (FMAResM[`FLEN-2:0] == ans[`FLEN-2:0]))))) begin
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$display( "%h %h %h %h %h %h %h Wrong ",X,Y, Z, FMAResM, ans, FMAFlgM, flags);
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if(FMAResM == 64'h8000000000000000) $display( "FMAResM=-zero ");
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if(XDenormE) $display( "xdenorm ");
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if(YDenormE) $display( "ydenorm ");
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if(ZDenormE) $display( "zdenorm ");
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if(FMAFlgM[4] != 0) $display( "invld ");
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if(FMAFlgM[2] != 0) $display( "ovrflw ");
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if(FMAFlgM[1] != 0) $display( "unflw ");
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if(FMAResM[`FLEN] && FMAResM[`FLEN-2:`NF] == {`NE{1'b1}} && FMAResM[`NF-1:0] == 0) $display( "FMAResM=-inf ");
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if(~FMAResM[`FLEN] && FMAResM[`FLEN-2:`NF] == {`NE{1'b1}} && FMAResM[`NF-1:0] == 0) $display( "FMAResM=+inf ");
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if(FMAResM[`FLEN-2:`NF] == {`NE{1'b1}} && FMAResM[`NF-1:0] != 0 && ~FMAResM[`NF-1]) $display( "FMAResM=sigNaN ");
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if(FMAResM[`FLEN-2:`NF] == {`NE{1'b1}} && FMAResM[`NF-1:0] != 0 && FMAResM[`NF-1]) $display( "FMAResM=qutNaN ");
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if(ans[`FLEN] && ans[`FLEN-2:`NF] == {`NE{1'b1}} && ans[`NF-1:0] == 0) $display( "ans=-inf ");
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if(~ans[`FLEN] && ans[`FLEN-2:`NF] == {`NE{1'b1}} && ans[`NF-1:0] == 0) $display( "ans=+inf ");
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if(ans[`FLEN-2:`NF] == {`NE{1'b1}} && ans[`NF-1:0] != 0 && ~ans[`NF-1]) $display( "ans=sigNaN ");
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if(ans[`FLEN-2:`NF] == {`NE{1'b1}} && ans[`NF-1:0] != 0 && ans[`NF-1]) $display( "ans=qutNaN ");
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errors = errors + 1;
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$stop;
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end
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if((FmtE==1'b0)&(FMAFlgM != flags[4:0] || (!wnan && (FMAResM != ans)) || (wnan && ansnan && ~(((XNaNE && (FMAResM[30:0] == {X[30:23],1'b1,X[21:0]})) || (YNaNE && (FMAResM[30:0] == {Y[30:23],1'b1,Y[21:0]})) || (ZNaNE && (FMAResM[30:0] == {Z[30:23],1'b1,Z[21:0]})) || (FMAResM[30:0] == ans[30:0]))) ))) begin
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$display( "%h %h %h %h %h %h %h Wrong ",X,Y, Z, FMAResM, ans, FMAFlgM, flags);
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if(FMAResM == 64'h8000000000000000) $display( "FMAResM=-zero ");
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if(~(|X[30:23]) && |X[22:0]) $display( "xdenorm ");
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if(~(|Y[30:23]) && |Y[22:0]) $display( "ydenorm ");
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if(~(|Z[30:23]) && |Z[22:0]) $display( "zdenorm ");
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if(FMAFlgM[4] != 0) $display( "invld ");
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if(FMAFlgM[2] != 0) $display( "ovrflw ");
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if(FMAFlgM[1] != 0) $display( "unflw ");
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if(FMAResM == 64'hFF80000000000000) $display( "FMAResM=-inf ");
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if(FMAResM == 64'h7F80000000000000) $display( "FMAResM=+inf ");
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if(&FMAResM[30:23] && |FMAResM[22:0] && ~FMAResM[22]) $display( "FMAResM=sigNaN ");
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if(&FMAResM[30:23] && |FMAResM[22:0] && FMAResM[22] ) $display( "FMAResM=qutNaN ");
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if(ans == 64'hFF80000000000000) $display( "ans=-inf ");
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if(ans == 64'h7F80000000000000) $display( "ans=+inf ");
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if(&ans[30:23] && |ans[22:0] && ~ans[22] ) $display( "ans=sigNaN ");
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if(&ans[30:23] && |ans[22:0] && ans[22]) $display( "ans=qutNaN ");
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errors = errors + 1;
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//if (errors == 10)
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$stop;
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end
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vectornum = vectornum + 1;
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if (testvectors[vectornum] === 194'bx) begin
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$display("%d tests completed with %d errors", vectornum, errors);
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$stop;
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end
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end
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endmodule
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3
wally-pipelined/fpu-testfloat/FMA/tbgen/test_gen.sh
Executable file
3
wally-pipelined/fpu-testfloat/FMA/tbgen/test_gen.sh
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@ -0,0 +1,3 @@
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testfloat_gen f32_mulAdd -tininessafter -n 6133248 -rnear_even -seed 113355 -level 1 > testFloat
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tr -d ' ' < testFloat > testFloatNoSpace
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@ -246,7 +246,7 @@ module fpuaddcvt1 (
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// Finds normal underflow result to determine whether to round final exponent down
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//***KEP used to be (AddSumE == 16'h0) I am unsure what it's supposed to be
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assign AddNormOvflowE = (AddDenormInE & (AddSumE == 64'h0) & (AddOpANormE | AddOpBNormE) & ~FOpCtrlE[0]) ? 1'b1 : (AddSumE[63] ? AddSumTcE[52] : AddSumE[52]);
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// assign AddNormOvflowE = (AddDenormInE & (AddSumE == 64'h0) & (AddOpANormE | AddOpBNormE) & ~FOpCtrlE[0]) ? 1'b1 : (AddSumE[63] ? AddSumTcE[52] : AddSumE[52]);
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endmodule // fpadd
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@ -1,6 +1,6 @@
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//`include "wally-config.vh"
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`include "../../config/rv64icfd/wally-config.vh"
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`include "wally-config.vh"
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// `include "../../config/rv64icfd/wally-config.vh"
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module fcvt (
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input logic XSgnE, // X's sign
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input logic [10:0] XExpE, // X's exponent
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