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FADD and FSUB imperas tests pass

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This commit is contained in:
Katherine Parry 2021-05-26 12:33:33 -04:00
parent bb99480fca
commit 309e6c3dc1
5 changed files with 7 additions and 7 deletions
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2
wally-pipelined/src/fpu/fctrl.sv
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@ -192,7 +192,7 @@ module fctrl (
// fcvt.d.wu = 1111 // fcvt.d.wu = 1111
// fcvt.d.s = 1000 // fcvt.d.s = 1000
// { is double and not add/sub, is to/from int, is to int or float to double, is unsigned or sub // { is double and not add/sub, is to/from int, is to int or float to double, is unsigned or sub
3'b100 : begin FOpCtrlD = {Funct7D[0]&Funct7D[5], Funct7D[6], Funct7D[3] | (~Funct7D[6]&Funct7D[5]&~Funct7D[0]), Rs2D[0]|(Funct7D[2]&~Funct7D[5])}; FInput2UsedD = ~Funct7D[5]; end 3'b100 : begin FOpCtrlD = {Funct7D[0]&Funct7D[5], Funct7D[6], Funct7D[3] | (~Funct7D[6]&Funct7D[5]&~Funct7D[0]), (Rs2D[0]&Funct7D[5])|(Funct7D[2]&~Funct7D[5])}; FInput2UsedD = ~Funct7D[5]; end
// classify {?, ?, ?, ?} // classify {?, ?, ?, ?}
3'b101 : begin FOpCtrlD = 4'b0; FInput2UsedD = 1'b0; end 3'b101 : begin FOpCtrlD = 4'b0; FInput2UsedD = 1'b0; end
// output SrcAW // output SrcAW

2
wally-pipelined/src/fpu/fpu.sv
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@ -353,7 +353,7 @@ module fpu (
flopenrc #(1) EMRegAdd12(clk, reset, PipeClearEM, PipeEnableEM, AddConvertE, AddConvertM); flopenrc #(1) EMRegAdd12(clk, reset, PipeClearEM, PipeEnableEM, AddConvertE, AddConvertM);
flopenrc #(1) EMRegAdd13(clk, reset, PipeClearEM, PipeEnableEM, AddSwapE, AddSwapM); flopenrc #(1) EMRegAdd13(clk, reset, PipeClearEM, PipeEnableEM, AddSwapE, AddSwapM);
flopenrc #(1) EMRegAdd14(clk, reset, PipeClearEM, PipeEnableEM, AddNormOvflowE, AddNormOvflowM); flopenrc #(1) EMRegAdd14(clk, reset, PipeClearEM, PipeEnableEM, AddNormOvflowE, AddNormOvflowM);
flopenrc #(1) EMRegAdd15(clk, reset, PipeClearEM, PipeEnableEM, AddSignAE, AddSignM); flopenrc #(1) EMRegAdd15(clk, reset, PipeClearEM, PipeEnableEM, AddSignAE, AddSignAM);
flopenrc #(64) EMRegAdd16(clk, reset, PipeClearEM, PipeEnableEM, AddFloat1E, AddFloat1M); flopenrc #(64) EMRegAdd16(clk, reset, PipeClearEM, PipeEnableEM, AddFloat1E, AddFloat1M);
flopenrc #(64) EMRegAdd17(clk, reset, PipeClearEM, PipeEnableEM, AddFloat2E, AddFloat2M); flopenrc #(64) EMRegAdd17(clk, reset, PipeClearEM, PipeEnableEM, AddFloat2E, AddFloat2M);
flopenrc #(12) EMRegAdd18(clk, reset, PipeClearEM, PipeEnableEM, AddExp1DenormE, AddExp1DenormM); flopenrc #(12) EMRegAdd18(clk, reset, PipeClearEM, PipeEnableEM, AddExp1DenormE, AddExp1DenormM);

2
wally-pipelined/src/fpu/fpuaddcvt1.sv
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@ -108,7 +108,7 @@ module fpuaddcvt1 (AddSumE, AddSumTcE, AddSelInvE, AddExpPostSumE, AddCorrSignE,
assign zeroB = FOpCtrlE[2] | FOpCtrlE[1]; assign zeroB = FOpCtrlE[2] | FOpCtrlE[1];
// Swapped operands if zeroB is not one and exp1 < exp2. // Swapped operands if zeroB is not one and exp1 < exp2.
// SwapFmtEg causes exp2 to be used for the result exponent. // Swapping causes exp2 to be used for the result exponent.
// Only the exponent of the larger operand is used to determine // Only the exponent of the larger operand is used to determine
// the final result. // the final result.
assign AddSwapE = exp_diff1[11] & ~zeroB; assign AddSwapE = exp_diff1[11] & ~zeroB;

2
wally-pipelined/src/fpu/fpuaddcvt2.sv
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@ -56,7 +56,7 @@ module fpuaddcvt2 (FAddResultM, FAddFlagsM, AddDenormM, AddSumM, AddSumTcM, AddS
output AddDenormM; // AddDenormM on input or output output AddDenormM; // AddDenormM on input or output
wire P; wire P;
assign P = FmtM | FOpCtrlM[2]; assign P = ~FmtM | FOpCtrlM[2];
wire [10:0] exp_pre; wire [10:0] exp_pre;
wire [63:0] Result; wire [63:0] Result;

6
wally-pipelined/testbench/testbench-imperas.sv
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@ -118,7 +118,7 @@ string tests32f[] = '{
}; };
string tests64d[] = '{ string tests64d[] = '{
// "rv64d/I-FADD-D-01", "2000", "rv64d/I-FADD-D-01", "2000",
// "rv64d/I-FCLASS-D-01", "2000", // "rv64d/I-FCLASS-D-01", "2000",
// "rv64d/I-FCVT-D-L-01", "2000", // "rv64d/I-FCVT-D-L-01", "2000",
// "rv64d/I-FCVT-D-LU-01", "2000", // "rv64d/I-FCVT-D-LU-01", "2000",
@ -142,14 +142,14 @@ string tests32f[] = '{
// "rv64d/I-FMSUB-D-01", "2000", // "rv64d/I-FMSUB-D-01", "2000",
// "rv64d/I-FMUL-D-01", "2000", // "rv64d/I-FMUL-D-01", "2000",
"rv64d/I-FMV-D-X-01", "2000", "rv64d/I-FMV-D-X-01", "2000",
"rv64d/I-FMV-X-D-01", "2000" "rv64d/I-FMV-X-D-01", "2000",
// "rv64d/I-FNMADD-D-01", "2000", // "rv64d/I-FNMADD-D-01", "2000",
// "rv64d/I-FNMSUB-D-01", "2000", // "rv64d/I-FNMSUB-D-01", "2000",
// "rv64d/I-FSGNJ-D-01", "2000", // "rv64d/I-FSGNJ-D-01", "2000",
// "rv64d/I-FSGNJN-D-01", "2000", // "rv64d/I-FSGNJN-D-01", "2000",
// "rv64d/I-FSGNJX-D-01", "2000", // "rv64d/I-FSGNJX-D-01", "2000",
// "rv64d/I-FSQRTD-01", "2000", // "rv64d/I-FSQRTD-01", "2000",
// "rv64d/I-FSUB-D-01", "2000" "rv64d/I-FSUB-D-01", "2000"
}; };
string tests64a[] = '{ string tests64a[] = '{