Xavi/cvw
1
0
Fork 0
forked from Github_Repos/cvw
Code Issues Pull Requests Packages Projects Releases Wiki Activity

Added support to print the gprs.

Browse Source
This commit is contained in:
Ross Thompson 2023-01-12 16:09:30 -06:00
parent 4733b787f8
commit 2e622c9860
1 changed files with 65 additions and 48 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

47
pipelined/testbench/common/rvvitrace.sv
View File

@ -3,6 +3,10 @@
`define NUM_REGS 32 `define NUM_REGS 32
`define NUM_CSRS 4096 `define NUM_CSRS 4096
`define PRINT_PC_INSTR 1
`define PRINT_MOST 1
`define PRINT_ALL 0
module rvviTrace #( module rvviTrace #(
parameter int ILEN = `XLEN, // Instruction length in bits parameter int ILEN = `XLEN, // Instruction length in bits
parameter int XLEN = `XLEN, // GPR length in bits parameter int XLEN = `XLEN, // GPR length in bits
@ -30,7 +34,7 @@ module rvviTrace #(
logic [4:0] rf_a3; logic [4:0] rf_a3;
logic rf_we3; logic rf_we3;
logic [`XLEN-1:0] frf[32]; logic [`XLEN-1:0] frf[32];
logic [31:0] frf_wb; logic [`NUM_REGS-1:0] frf_wb;
logic [4:0] frf_a4; logic [4:0] frf_a4;
logic frf_we4; logic frf_we4;
@ -39,6 +43,7 @@ module rvviTrace #(
// tracer signals // tracer signals
logic clk; logic clk;
logic valid; logic valid;
logic [63:0] order [(NHART-1):0][(RETIRE-1):0];
logic [ILEN-1:0] insn [(NHART-1):0][(RETIRE-1):0]; logic [ILEN-1:0] insn [(NHART-1):0][(RETIRE-1):0];
logic [(XLEN-1):0] pc_rdata [(NHART-1):0][(RETIRE-1):0]; logic [(XLEN-1):0] pc_rdata [(NHART-1):0][(RETIRE-1):0];
logic [(XLEN-1):0] pc_wdata [(NHART-1):0][(RETIRE-1):0]; logic [(XLEN-1):0] pc_wdata [(NHART-1):0][(RETIRE-1):0];
@ -47,13 +52,13 @@ module rvviTrace #(
logic intr [(NHART-1):0][(RETIRE-1):0]; logic intr [(NHART-1):0][(RETIRE-1):0];
logic [1:0] mode [(NHART-1):0][(RETIRE-1):0]; logic [1:0] mode [(NHART-1):0][(RETIRE-1):0];
logic [1:0] ixl [(NHART-1):0][(RETIRE-1):0]; logic [1:0] ixl [(NHART-1):0][(RETIRE-1):0];
logic [31:0][(XLEN-1):0] x_wdata [(NHART-1):0][(RETIRE-1):0]; logic [`NUM_REGS-1:0][(XLEN-1):0] x_wdata [(NHART-1):0][(RETIRE-1):0];
logic [31:0] x_wb [(NHART-1):0][(RETIRE-1):0]; logic [`NUM_REGS-1:0] x_wb [(NHART-1):0][(RETIRE-1):0];
logic [31:0][(XLEN-1):0] f_wdata [(NHART-1):0][(RETIRE-1):0]; logic [`NUM_REGS-1:0][(XLEN-1):0] f_wdata [(NHART-1):0][(RETIRE-1):0];
logic [31:0] f_wb [(NHART-1):0][(RETIRE-1):0]; logic [`NUM_REGS-1:0] f_wb [(NHART-1):0][(RETIRE-1):0];
assign clk = testbench.dut.clk; assign clk = testbench.dut.clk;
// assign InstrValidF = testbench.dut.core.ieu.InstrValidF; // not needed yet // assign InstrValidF = testbench.dut.core.ieu.InstrValidF; // not needed yet
assign InstrValidD = testbench.dut.core.ieu.c.InstrValidD; assign InstrValidD = testbench.dut.core.ieu.c.InstrValidD;
assign InstrValidE = testbench.dut.core.ieu.c.InstrValidE; assign InstrValidE = testbench.dut.core.ieu.c.InstrValidE;
assign InstrValidM = testbench.dut.core.ieu.InstrValidM; assign InstrValidM = testbench.dut.core.ieu.InstrValidM;
@ -73,6 +78,7 @@ module rvviTrace #(
assign FlushW = testbench.dut.core.FlushW; assign FlushW = testbench.dut.core.FlushW;
assign TrapM = testbench.dut.core.TrapM; assign TrapM = testbench.dut.core.TrapM;
assign HaltM = testbench.DCacheFlushStart; assign HaltM = testbench.DCacheFlushStart;
assign PrivilegeModeW = testbench.dut.core.priv.priv.privmode.PrivilegeModeW;
assign STATUS_SXL = testbench.dut.core.priv.priv.csr.csrsr.STATUS_SXL; assign STATUS_SXL = testbench.dut.core.priv.priv.csr.csrsr.STATUS_SXL;
assign STATUS_UXL = testbench.dut.core.priv.priv.csr.csrsr.STATUS_UXL; assign STATUS_UXL = testbench.dut.core.priv.priv.csr.csrsr.STATUS_UXL;
@ -121,26 +127,37 @@ module rvviTrace #(
assign halt[0][0] = HaltW; assign halt[0][0] = HaltW;
assign intr[0][0] = '0; // *** first retired instruction of trap handler. Not sure how i'm going to get this yet. assign intr[0][0] = '0; // *** first retired instruction of trap handler. Not sure how i'm going to get this yet.
assign mode[0][0] = PrivilegeModeW; assign mode[0][0] = PrivilegeModeW;
assign ixl[0][0] = PrivilegeModeW == 2'b11 ? `XLEN : assign ixl[0][0] = PrivilegeModeW == 2'b11 ? 2'b10 :
PrivilegeModeW == 2'b01 ? STATUS_SXL : STATUS_UXL; PrivilegeModeW == 2'b01 ? STATUS_SXL : STATUS_UXL;
assign pc_wdata[0][0] = ~FlushW ? PCM : assign pc_wdata[0][0] = ~FlushW ? PCM :
~FlushM ? PCE : ~FlushM ? PCE :
~FlushE ? PCD : ~FlushE ? PCD :
~FlushD ? PCF : PCNextF; ~FlushD ? PCF : PCNextF;
for(index = 0; index < NUMREGS; index += 1) begin for(index = 0; index < `NUM_REGS; index += 1) begin
assign x_wdata[index][0][0] = rf[index]; assign x_wdata[0][0][index] = rf[index];
assign x_wb[index][0][0] = rf_wb[index]; assign x_wb[0][0][index] = rf_wb[index];
assign f_wdata[index][0][0] = frf[index]; assign f_wdata[0][0][index] = frf[index];
assign f_wb[index][0][0] = frf_wb[index]; assign f_wb[0][0][index] = frf_wb[index];
end end
integer index2;
always_ff @(posedge clk) begin always_ff @(posedge clk) begin
if(valid) begin if(valid) begin
$display("PC = %08x, insn = %08x, trap = %1d, halt = %1d", pc_rdata[0][0], insn[0][0], trap[0][0], halt[0][0]); if(`PRINT_PC_INSTR & !(`PRINT_ALL | `PRINT_MOST))
$display("PC = %08x, insn = %08x", pc_rdata[0][0], insn[0][0]);
else if(`PRINT_MOST & !`PRINT_ALL)
$display("PC = %08x, insn = %08x, trap = %1d, halt = %1d, mode = %1x, ixl = %1x, pc_wdata = %08x, x%02d = %08x", pc_rdata[0][0], insn[0][0], trap[0][0], halt[0][0], mode[0][0], ixl[0][0], pc_wdata[0][0], rf_a3, x_wdata[0][0][rf_a3]);
else if(`PRINT_ALL) begin
$display("PC = %08x, insn = %08x, trap = %1d, halt = %1d, mode = %1x, ixl = %1x, pc_wdata = %08x", pc_rdata[0][0], insn[0][0], trap[0][0], halt[0][0], mode[0][0], ixl[0][0], pc_wdata[0][0]);
for(index2 = 0; index2 < `NUM_REGS; index2 += 1) begin
$display("x%02d = %08x", index2, x_wdata[0][0][index2]);
end
for(index2 = 0; index2 < `NUM_REGS; index2 += 1) begin
$display("f%02d = %08x", index2, f_wdata[0][0][index2]);
end
end
end end
if(HaltW) $stop(); if(HaltW) $stop();
end end