forked from Github_Repos/cvw
Added support to print the gprs.
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4733b787f8
commit
2e622c9860
@ -3,6 +3,10 @@
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`define NUM_REGS 32
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`define NUM_REGS 32
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`define NUM_CSRS 4096
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`define NUM_CSRS 4096
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`define PRINT_PC_INSTR 1
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`define PRINT_MOST 1
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`define PRINT_ALL 0
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module rvviTrace #(
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module rvviTrace #(
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parameter int ILEN = `XLEN, // Instruction length in bits
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parameter int ILEN = `XLEN, // Instruction length in bits
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parameter int XLEN = `XLEN, // GPR length in bits
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parameter int XLEN = `XLEN, // GPR length in bits
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@ -30,7 +34,7 @@ module rvviTrace #(
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logic [4:0] rf_a3;
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logic [4:0] rf_a3;
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logic rf_we3;
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logic rf_we3;
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logic [`XLEN-1:0] frf[32];
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logic [`XLEN-1:0] frf[32];
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logic [31:0] frf_wb;
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logic [`NUM_REGS-1:0] frf_wb;
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logic [4:0] frf_a4;
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logic [4:0] frf_a4;
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logic frf_we4;
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logic frf_we4;
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@ -39,6 +43,7 @@ module rvviTrace #(
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// tracer signals
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// tracer signals
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logic clk;
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logic clk;
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logic valid;
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logic valid;
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logic [63:0] order [(NHART-1):0][(RETIRE-1):0];
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logic [ILEN-1:0] insn [(NHART-1):0][(RETIRE-1):0];
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logic [ILEN-1:0] insn [(NHART-1):0][(RETIRE-1):0];
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logic [(XLEN-1):0] pc_rdata [(NHART-1):0][(RETIRE-1):0];
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logic [(XLEN-1):0] pc_rdata [(NHART-1):0][(RETIRE-1):0];
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logic [(XLEN-1):0] pc_wdata [(NHART-1):0][(RETIRE-1):0];
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logic [(XLEN-1):0] pc_wdata [(NHART-1):0][(RETIRE-1):0];
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@ -47,13 +52,13 @@ module rvviTrace #(
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logic intr [(NHART-1):0][(RETIRE-1):0];
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logic intr [(NHART-1):0][(RETIRE-1):0];
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logic [1:0] mode [(NHART-1):0][(RETIRE-1):0];
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logic [1:0] mode [(NHART-1):0][(RETIRE-1):0];
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logic [1:0] ixl [(NHART-1):0][(RETIRE-1):0];
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logic [1:0] ixl [(NHART-1):0][(RETIRE-1):0];
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logic [31:0][(XLEN-1):0] x_wdata [(NHART-1):0][(RETIRE-1):0];
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logic [`NUM_REGS-1:0][(XLEN-1):0] x_wdata [(NHART-1):0][(RETIRE-1):0];
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logic [31:0] x_wb [(NHART-1):0][(RETIRE-1):0];
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logic [`NUM_REGS-1:0] x_wb [(NHART-1):0][(RETIRE-1):0];
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logic [31:0][(XLEN-1):0] f_wdata [(NHART-1):0][(RETIRE-1):0];
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logic [`NUM_REGS-1:0][(XLEN-1):0] f_wdata [(NHART-1):0][(RETIRE-1):0];
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logic [31:0] f_wb [(NHART-1):0][(RETIRE-1):0];
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logic [`NUM_REGS-1:0] f_wb [(NHART-1):0][(RETIRE-1):0];
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assign clk = testbench.dut.clk;
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assign clk = testbench.dut.clk;
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// assign InstrValidF = testbench.dut.core.ieu.InstrValidF; // not needed yet
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// assign InstrValidF = testbench.dut.core.ieu.InstrValidF; // not needed yet
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assign InstrValidD = testbench.dut.core.ieu.c.InstrValidD;
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assign InstrValidD = testbench.dut.core.ieu.c.InstrValidD;
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assign InstrValidE = testbench.dut.core.ieu.c.InstrValidE;
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assign InstrValidE = testbench.dut.core.ieu.c.InstrValidE;
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assign InstrValidM = testbench.dut.core.ieu.InstrValidM;
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assign InstrValidM = testbench.dut.core.ieu.InstrValidM;
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@ -73,6 +78,7 @@ module rvviTrace #(
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assign FlushW = testbench.dut.core.FlushW;
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assign FlushW = testbench.dut.core.FlushW;
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assign TrapM = testbench.dut.core.TrapM;
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assign TrapM = testbench.dut.core.TrapM;
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assign HaltM = testbench.DCacheFlushStart;
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assign HaltM = testbench.DCacheFlushStart;
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assign PrivilegeModeW = testbench.dut.core.priv.priv.privmode.PrivilegeModeW;
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assign STATUS_SXL = testbench.dut.core.priv.priv.csr.csrsr.STATUS_SXL;
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assign STATUS_SXL = testbench.dut.core.priv.priv.csr.csrsr.STATUS_SXL;
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assign STATUS_UXL = testbench.dut.core.priv.priv.csr.csrsr.STATUS_UXL;
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assign STATUS_UXL = testbench.dut.core.priv.priv.csr.csrsr.STATUS_UXL;
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@ -121,26 +127,37 @@ module rvviTrace #(
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assign halt[0][0] = HaltW;
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assign halt[0][0] = HaltW;
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assign intr[0][0] = '0; // *** first retired instruction of trap handler. Not sure how i'm going to get this yet.
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assign intr[0][0] = '0; // *** first retired instruction of trap handler. Not sure how i'm going to get this yet.
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assign mode[0][0] = PrivilegeModeW;
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assign mode[0][0] = PrivilegeModeW;
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assign ixl[0][0] = PrivilegeModeW == 2'b11 ? `XLEN :
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assign ixl[0][0] = PrivilegeModeW == 2'b11 ? 2'b10 :
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PrivilegeModeW == 2'b01 ? STATUS_SXL : STATUS_UXL;
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PrivilegeModeW == 2'b01 ? STATUS_SXL : STATUS_UXL;
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assign pc_wdata[0][0] = ~FlushW ? PCM :
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assign pc_wdata[0][0] = ~FlushW ? PCM :
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~FlushM ? PCE :
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~FlushM ? PCE :
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~FlushE ? PCD :
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~FlushE ? PCD :
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~FlushD ? PCF : PCNextF;
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~FlushD ? PCF : PCNextF;
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for(index = 0; index < NUMREGS; index += 1) begin
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for(index = 0; index < `NUM_REGS; index += 1) begin
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assign x_wdata[index][0][0] = rf[index];
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assign x_wdata[0][0][index] = rf[index];
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assign x_wb[index][0][0] = rf_wb[index];
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assign x_wb[0][0][index] = rf_wb[index];
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assign f_wdata[index][0][0] = frf[index];
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assign f_wdata[0][0][index] = frf[index];
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assign f_wb[index][0][0] = frf_wb[index];
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assign f_wb[0][0][index] = frf_wb[index];
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end
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end
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integer index2;
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always_ff @(posedge clk) begin
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always_ff @(posedge clk) begin
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if(valid) begin
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if(valid) begin
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$display("PC = %08x, insn = %08x, trap = %1d, halt = %1d", pc_rdata[0][0], insn[0][0], trap[0][0], halt[0][0]);
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if(`PRINT_PC_INSTR & !(`PRINT_ALL | `PRINT_MOST))
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$display("PC = %08x, insn = %08x", pc_rdata[0][0], insn[0][0]);
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else if(`PRINT_MOST & !`PRINT_ALL)
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$display("PC = %08x, insn = %08x, trap = %1d, halt = %1d, mode = %1x, ixl = %1x, pc_wdata = %08x, x%02d = %08x", pc_rdata[0][0], insn[0][0], trap[0][0], halt[0][0], mode[0][0], ixl[0][0], pc_wdata[0][0], rf_a3, x_wdata[0][0][rf_a3]);
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else if(`PRINT_ALL) begin
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$display("PC = %08x, insn = %08x, trap = %1d, halt = %1d, mode = %1x, ixl = %1x, pc_wdata = %08x", pc_rdata[0][0], insn[0][0], trap[0][0], halt[0][0], mode[0][0], ixl[0][0], pc_wdata[0][0]);
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for(index2 = 0; index2 < `NUM_REGS; index2 += 1) begin
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$display("x%02d = %08x", index2, x_wdata[0][0][index2]);
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end
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for(index2 = 0; index2 < `NUM_REGS; index2 += 1) begin
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$display("f%02d = %08x", index2, f_wdata[0][0][index2]);
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end
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end
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end
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end
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if(HaltW) $stop();
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if(HaltW) $stop();
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end
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end
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