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Added lock signal to ensure AHB speaks with the right bus

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slmnemo 2022-06-08 02:19:21 +00:00
parent 6d36150c3d
commit 2d76953d42
6 changed files with 36 additions and 22 deletions
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18
pipelined/src/ebu/ahblite.sv
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@ -45,6 +45,7 @@ module ahblite (
input logic IFUBusRead, input logic IFUBusRead,
output logic [`XLEN-1:0] IFUBusHRDATA, output logic [`XLEN-1:0] IFUBusHRDATA,
output logic IFUBusAck, output logic IFUBusAck,
output logic IFUBusLock,
input logic [2:0] IFUBurstType, input logic [2:0] IFUBurstType,
input logic [1:0] IFUTransType, input logic [1:0] IFUTransType,
input logic IFUBurstDone, input logic IFUBurstDone,
@ -59,6 +60,7 @@ module ahblite (
input logic [1:0] LSUTransType, input logic [1:0] LSUTransType,
input logic LSUBurstDone, input logic LSUBurstDone,
output logic LSUBusAck, output logic LSUBusAck,
output logic LSUBusLock,
// AHB-Lite external signals // AHB-Lite external signals
(* mark_debug = "true" *) input logic [`AHBW-1:0] HRDATA, (* mark_debug = "true" *) input logic [`AHBW-1:0] HRDATA,
(* mark_debug = "true" *) input logic HREADY, HRESP, (* mark_debug = "true" *) input logic HREADY, HRESP,
@ -116,21 +118,21 @@ module ahblite (
else NextBusState = IDLE; else NextBusState = IDLE;
MEMREAD: if (HREADY) NextBusState = MEMREADNEXT; MEMREAD: if (HREADY) NextBusState = MEMREADNEXT;
else NextBusState = MEMREAD; else NextBusState = MEMREAD;
MEMREADNEXT: if (LSUBurstDone & ~IFUBusRead) NextBusState = IDLE; MEMREADNEXT: if (LSUBurstDone & ~(IFUBusRead & ~HREADY)) NextBusState = IDLE;
else if (LSUBurstDone & IFUBusRead) NextBusState = INSTRREAD; else if (LSUBurstDone & IFUBusRead & HREADY) NextBusState = INSTRREAD;
else if (HREADY) NextBusState = MEMREADNEXT; else if (HREADY) NextBusState = MEMREADNEXT;
else NextBusState = MEMREAD; else NextBusState = MEMREAD;
MEMWRITE: if (HREADY) NextBusState = MEMWRITENEXT; MEMWRITE: if (HREADY) NextBusState = MEMWRITENEXT;
else NextBusState = MEMWRITE; else NextBusState = MEMWRITE;
MEMWRITENEXT: if (LSUBurstDone & ~IFUBusRead) NextBusState = IDLE; MEMWRITENEXT: if (LSUBurstDone & ~(IFUBusRead & ~HREADY)) NextBusState = IDLE;
else if (LSUBurstDone & IFUBusRead) NextBusState = INSTRREAD; else if (LSUBurstDone & IFUBusRead & HREADY) NextBusState = INSTRREAD;
else if (HREADY) NextBusState = MEMWRITENEXT; else if (HREADY) NextBusState = MEMWRITENEXT;
else NextBusState = MEMWRITE; else NextBusState = MEMWRITE;
INSTRREAD: if (HREADY) NextBusState = INSTRREADNEXT; INSTRREAD: if (HREADY) NextBusState = INSTRREADNEXT;
else NextBusState = INSTRREAD; else NextBusState = INSTRREAD;
INSTRREADNEXT: if (IFUBurstDone & ~LSUBusRead & ~LSUBusWrite) NextBusState = IDLE; INSTRREADNEXT: if (IFUBurstDone & ~LSUBusRead & ~LSUBusWrite) NextBusState = IDLE;
else if (IFUBurstDone & LSUBusRead) NextBusState = MEMREAD; else if (IFUBurstDone & LSUBusRead & HREADY) NextBusState = MEMREAD;
else if (IFUBurstDone & LSUBusWrite) NextBusState = MEMWRITE; else if (IFUBurstDone & LSUBusWrite & HREADY) NextBusState = MEMWRITE;
else if (HREADY) NextBusState = INSTRREADNEXT; else if (HREADY) NextBusState = INSTRREADNEXT;
else NextBusState = INSTRREAD; else NextBusState = INSTRREAD;
default: NextBusState = IDLE; default: NextBusState = IDLE;
@ -161,7 +163,7 @@ module ahblite (
assign HPROT = 4'b0011; // not used; see Section 3.7 assign HPROT = 4'b0011; // not used; see Section 3.7
assign HTRANS = SubsequentAccess ? 2'b11 : (NextBusState != IDLE) ? 2'b10 : 2'b00; // SEQ if not first read or write, NONSEQ if first read or write, IDLE otherwise assign HTRANS = (GrantData) ? LSUTransType : IFUTransType; // SEQ if not first read or write, NONSEQ if first read or write, IDLE otherwise
assign HMASTLOCK = 0; // no locking supported assign HMASTLOCK = 0; // no locking supported
assign HWRITE = (NextBusState == MEMWRITE) | (NextBusState == MEMWRITENEXT); assign HWRITE = (NextBusState == MEMWRITE) | (NextBusState == MEMWRITENEXT);
// delay write data by one cycle for // delay write data by one cycle for
@ -177,6 +179,8 @@ module ahblite (
assign IFUBusHRDATA = HRDATA; assign IFUBusHRDATA = HRDATA;
assign LSUBusHRDATA = HRDATA; assign LSUBusHRDATA = HRDATA;
assign IFUBusLock = (NextBusState == INSTRREAD) | (NextBusState == INSTRREADNEXT);
assign LSUBusLock = (NextBusState == MEMWRITENEXT) | (NextBusState == MEMREADNEXT) | (NextBusState == MEMREAD) | (NextBusState == MEMWRITE);
assign IFUBusAck = (BusState == INSTRREADNEXT); assign IFUBusAck = (BusState == INSTRREADNEXT);
assign LSUBusAck = (BusState == MEMREADNEXT) | (BusState == MEMWRITENEXT); assign LSUBusAck = (BusState == MEMREADNEXT) | (BusState == MEMWRITENEXT);

3
pipelined/src/ifu/ifu.sv
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@ -38,6 +38,7 @@ module ifu (
// Bus interface // Bus interface
(* mark_debug = "true" *) input logic [`XLEN-1:0] IFUBusHRDATA, (* mark_debug = "true" *) input logic [`XLEN-1:0] IFUBusHRDATA,
(* mark_debug = "true" *) input logic IFUBusAck, (* mark_debug = "true" *) input logic IFUBusAck,
(* mark_debug = "true" *) input logic IFUBusLock,
(* mark_debug = "true" *) output logic [`PA_BITS-1:0] IFUBusAdr, (* mark_debug = "true" *) output logic [`PA_BITS-1:0] IFUBusAdr,
(* mark_debug = "true" *) output logic IFUBusRead, (* mark_debug = "true" *) output logic IFUBusRead,
(* mark_debug = "true" *) output logic IFUStallF, (* mark_debug = "true" *) output logic IFUStallF,
@ -192,7 +193,7 @@ module ifu (
busdp #(WORDSPERLINE, LINELEN, LOGWPL, CACHE_ENABLED) busdp #(WORDSPERLINE, LINELEN, LOGWPL, CACHE_ENABLED)
busdp(.clk, .reset, busdp(.clk, .reset,
.LSUBusHRDATA(IFUBusHRDATA), .LSUBusAck(IFUBusAck), .LSUBusWrite(), .LSUBusWriteCrit(), .LSUBusHRDATA(IFUBusHRDATA), .LSUBusAck(IFUBusAck), .LSUBusLock(IFUBusLock), .LSUBusWrite(), .LSUBusWriteCrit(),
.LSUBusRead(IFUBusRead), .LSUBusSize(), .LSUBurstType(IFUBurstType), .LSUTransType(IFUTransType), .LSUBurstDone(IFUBurstDone), .LSUBusRead(IFUBusRead), .LSUBusSize(), .LSUBurstType(IFUBurstType), .LSUTransType(IFUTransType), .LSUBurstDone(IFUBurstDone),
.LSUFunct3M(3'b010), .LSUBusAdr(IFUBusAdr), .DCacheBusAdr(ICacheBusAdr), .LSUFunct3M(3'b010), .LSUBusAdr(IFUBusAdr), .DCacheBusAdr(ICacheBusAdr),
.WordCount(), .WordCount(),

3
pipelined/src/lsu/busdp.sv
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@ -40,6 +40,7 @@ module busdp #(parameter WORDSPERLINE, LINELEN, LOGWPL, CACHE_ENABLED)
// bus interface // bus interface
input logic [`XLEN-1:0] LSUBusHRDATA, input logic [`XLEN-1:0] LSUBusHRDATA,
input logic LSUBusAck, input logic LSUBusAck,
input logic LSUBusLock,
output logic LSUBusWrite, output logic LSUBusWrite,
output logic LSUBusRead, output logic LSUBusRead,
output logic [2:0] LSUBusSize, output logic [2:0] LSUBusSize,
@ -88,6 +89,6 @@ module busdp #(parameter WORDSPERLINE, LINELEN, LOGWPL, CACHE_ENABLED)
busfsm #(WordCountThreshold, LOGWPL, CACHE_ENABLED) busfsm( busfsm #(WordCountThreshold, LOGWPL, CACHE_ENABLED) busfsm(
.clk, .reset, .IgnoreRequest, .LSURWM, .DCacheFetchLine, .DCacheWriteLine, .clk, .reset, .IgnoreRequest, .LSURWM, .DCacheFetchLine, .DCacheWriteLine,
.LSUBusAck, .CPUBusy, .CacheableM, .BusStall, .LSUBusWrite, .LSUBusWriteCrit, .LSUBusRead, .LSUBusAck, .LSUBusLock, .CPUBusy, .CacheableM, .BusStall, .LSUBusWrite, .LSUBusWriteCrit, .LSUBusRead,
.LSUBurstType, .LSUTransType, .LSUBurstDone, .DCacheBusAck, .BusCommittedM, .SelUncachedAdr, .WordCount, .WordCountDelayed); .LSUBurstType, .LSUTransType, .LSUBurstDone, .DCacheBusAck, .BusCommittedM, .SelUncachedAdr, .WordCount, .WordCountDelayed);
endmodule endmodule

13
pipelined/src/lsu/busfsm.sv
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@ -41,6 +41,7 @@ module busfsm #(parameter integer WordCountThreshold,
input logic DCacheFetchLine, input logic DCacheFetchLine,
input logic DCacheWriteLine, input logic DCacheWriteLine,
input logic LSUBusAck, input logic LSUBusAck,
input logic LSUBusLock,
input logic CPUBusy, input logic CPUBusy,
input logic CacheableM, input logic CacheableM,
@ -97,7 +98,7 @@ module busfsm #(parameter integer WordCountThreshold,
assign NextWordCount = WordCount + 1'b1; assign NextWordCount = WordCount + 1'b1;
assign WordCountFlag = (WordCountDelayed == WordCountThreshold[LOGWPL-1:0]); assign WordCountFlag = (WordCountDelayed == WordCountThreshold[LOGWPL-1:0]);
assign CntEn = PreCntEn & LSUBusAck | (DCacheFetchLine | DCacheWriteLine); assign CntEn = PreCntEn & LSUBusAck | ((DCacheFetchLine | DCacheWriteLine) & LSUBusLock);
assign UnCachedAccess = ~CACHE_ENABLED | ~CacheableM; assign UnCachedAccess = ~CACHE_ENABLED | ~CacheableM;
@ -133,16 +134,16 @@ module busfsm #(parameter integer WordCountThreshold,
always_comb begin always_comb begin
case(WordCountThreshold) case(WordCountThreshold)
4: LocalBurstType = 3'b010; // WRAP4 3: LocalBurstType = 3'b011; // INCR4
8: LocalBurstType = 3'b100; // WRAP8 7: LocalBurstType = 3'b101; // INCR8
16: LocalBurstType = 3'b110; // WRAP16 15: LocalBurstType = 3'b111; // INCR16
default: LocalBurstType = 3'b000; // No Burst default: LocalBurstType = 3'b000; // No Burst
endcase // *** This isn't working, ask someone for help. endcase
end end
assign LSUBurstType = (UnCachedAccess) ? 3'b0 : LocalBurstType ; // Don't want to use burst when doing an Uncached Access assign LSUBurstType = (UnCachedAccess) ? 3'b0 : LocalBurstType ; // Don't want to use burst when doing an Uncached Access
assign LSUBurstDone = (UnCachedAccess) ? LSUBusAck : WordCountFlag & LSUBusAck; assign LSUBurstDone = (UnCachedAccess) ? LSUBusAck : WordCountFlag & LSUBusAck;
assign LSUTransType = (|WordCount) ? 2'b11 : (LSUBusRead | LSUBusWrite) ? 2'b10 : 2'b00; assign LSUTransType = (|WordCount | |WordCountDelayed) ? 2'b11 : (LSUBusRead | LSUBusWrite) ? 2'b10 : 2'b00;
assign CntReset = BusCurrState == STATE_BUS_READY & ~(DCacheFetchLine | DCacheWriteLine); assign CntReset = BusCurrState == STATE_BUS_READY & ~(DCacheFetchLine | DCacheWriteLine);
assign BusStall = (BusCurrState == STATE_BUS_READY & ~IgnoreRequest & ((UnCachedAccess & (|LSURWM)) | DCacheFetchLine | DCacheWriteLine)) | assign BusStall = (BusCurrState == STATE_BUS_READY & ~IgnoreRequest & ((UnCachedAccess & (|LSURWM)) | DCacheFetchLine | DCacheWriteLine)) |

3
pipelined/src/lsu/lsu.sv
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@ -66,6 +66,7 @@ module lsu (
(* mark_debug = "true" *) output logic LSUBusRead, (* mark_debug = "true" *) output logic LSUBusRead,
(* mark_debug = "true" *) output logic LSUBusWrite, (* mark_debug = "true" *) output logic LSUBusWrite,
(* mark_debug = "true" *) input logic LSUBusAck, (* mark_debug = "true" *) input logic LSUBusAck,
(* mark_debug = "true" *) input logic LSUBusLock,
(* mark_debug = "true" *) input logic [`XLEN-1:0] LSUBusHRDATA, (* mark_debug = "true" *) input logic [`XLEN-1:0] LSUBusHRDATA,
(* mark_debug = "true" *) output logic [`XLEN-1:0] LSUBusHWDATA, (* mark_debug = "true" *) output logic [`XLEN-1:0] LSUBusHWDATA,
(* mark_debug = "true" *) output logic [2:0] LSUBusSize, (* mark_debug = "true" *) output logic [2:0] LSUBusSize,
@ -214,7 +215,7 @@ module lsu (
busdp #(WORDSPERLINE, LINELEN, LOGWPL, CACHE_ENABLED) busdp( busdp #(WORDSPERLINE, LINELEN, LOGWPL, CACHE_ENABLED) busdp(
.clk, .reset, .clk, .reset,
.LSUBusHRDATA, .LSUBusAck, .LSUBusWrite, .LSUBusRead, .LSUBusSize, .LSUBurstType, .LSUTransType, .LSUBurstDone, .LSUBusHRDATA, .LSUBusAck, .LSUBusLock, .LSUBusWrite, .LSUBusRead, .LSUBusSize, .LSUBurstType, .LSUTransType, .LSUBurstDone,
.WordCount, .LSUBusWriteCrit, .WordCount, .LSUBusWriteCrit,
.LSUFunct3M, .LSUBusAdr, .DCacheBusAdr, .DCacheFetchLine, .LSUFunct3M, .LSUBusAdr, .DCacheBusAdr, .DCacheFetchLine,
.DCacheWriteLine, .DCacheBusAck, .DCacheBusWriteData, .LSUPAdrM, .DCacheWriteLine, .DCacheBusAck, .DCacheBusWriteData, .LSUPAdrM,

18
pipelined/src/wally/wallypipelinedcore.sv
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@ -135,7 +135,7 @@ module wallypipelinedcore (
logic [`PA_BITS-1:0] IFUBusAdr; logic [`PA_BITS-1:0] IFUBusAdr;
logic [`XLEN-1:0] IFUBusHRDATA; logic [`XLEN-1:0] IFUBusHRDATA;
logic IFUBusRead; logic IFUBusRead;
logic IFUBusAck; logic IFUBusAck, IFUBusLock;
logic [2:0] IFUBurstType; logic [2:0] IFUBurstType;
logic [1:0] IFUTransType; logic [1:0] IFUTransType;
logic IFUBurstDone; logic IFUBurstDone;
@ -144,7 +144,7 @@ module wallypipelinedcore (
logic [`PA_BITS-1:0] LSUBusAdr; logic [`PA_BITS-1:0] LSUBusAdr;
logic LSUBusRead; logic LSUBusRead;
logic LSUBusWrite; logic LSUBusWrite;
logic LSUBusAck; logic LSUBusAck, LSUBusLock;
logic [`XLEN-1:0] LSUBusHRDATA; logic [`XLEN-1:0] LSUBusHRDATA;
logic [`XLEN-1:0] LSUBusHWDATA; logic [`XLEN-1:0] LSUBusHWDATA;
@ -173,7 +173,7 @@ module wallypipelinedcore (
.StallF, .StallD, .StallE, .StallM, .StallF, .StallD, .StallE, .StallM,
.FlushF, .FlushD, .FlushE, .FlushM, .FlushF, .FlushD, .FlushE, .FlushM,
// Fetch // Fetch
.IFUBusHRDATA, .IFUBusAck, .PCF, .IFUBusAdr, .IFUBusHRDATA, .IFUBusAck, .IFUBusLock, .PCF, .IFUBusAdr,
.IFUBusRead, .IFUStallF, .IFUBurstType, .IFUTransType, .IFUBurstDone, .IFUBusRead, .IFUStallF, .IFUBurstType, .IFUTransType, .IFUBurstDone,
.ICacheAccess, .ICacheMiss, .ICacheAccess, .ICacheMiss,
@ -254,7 +254,7 @@ module wallypipelinedcore (
.IEUAdrE, .IEUAdrM, .WriteDataE, .IEUAdrE, .IEUAdrM, .WriteDataE,
.ReadDataM, .FlushDCacheM, .ReadDataM, .FlushDCacheM,
// connected to ahb (all stay the same) // connected to ahb (all stay the same)
.LSUBusAdr, .LSUBusRead, .LSUBusWrite, .LSUBusAck, .LSUBusAdr, .LSUBusRead, .LSUBusWrite, .LSUBusAck, .LSUBusLock,
.LSUBusHRDATA, .LSUBusHWDATA, .LSUBusSize, .LSUBurstType, .LSUTransType, .LSUBurstDone, .LSUBusHRDATA, .LSUBusHWDATA, .LSUBusSize, .LSUBurstType, .LSUTransType, .LSUBurstDone,
// connect to csr or privilege and stay the same. // connect to csr or privilege and stay the same.
@ -286,8 +286,13 @@ module wallypipelinedcore (
ahblite ebu(// IFU connections ahblite ebu(// IFU connections
.clk, .reset, .clk, .reset,
.UnsignedLoadM(1'b0), .AtomicMaskedM(2'b00), .UnsignedLoadM(1'b0), .AtomicMaskedM(2'b00),
.IFUBusAdr, .IFUBusAdr, .IFUBusRead,
.IFUBusRead, .IFUBusHRDATA, .IFUBusAck, .IFUBurstType, .IFUTransType, .IFUBurstDone, .IFUBusHRDATA,
.IFUBurstType,
.IFUTransType,
.IFUBurstDone,
.IFUBusAck,
.IFUBusLock,
// Signals from Data Cache // Signals from Data Cache
.LSUBusAdr, .LSUBusRead, .LSUBusWrite, .LSUBusHWDATA, .LSUBusAdr, .LSUBusRead, .LSUBusWrite, .LSUBusHWDATA,
.LSUBusHRDATA, .LSUBusHRDATA,
@ -296,6 +301,7 @@ module wallypipelinedcore (
.LSUTransType, .LSUTransType,
.LSUBurstDone, .LSUBurstDone,
.LSUBusAck, .LSUBusAck,
.LSUBusLock,
.HRDATA, .HREADY, .HRESP, .HCLK, .HRESETn, .HRDATA, .HREADY, .HRESP, .HCLK, .HRESETn,
.HADDR, .HWDATA, .HWRITE, .HSIZE, .HBURST, .HADDR, .HWDATA, .HWRITE, .HSIZE, .HBURST,