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Simplified BTB by removing the valid bit. the instruction class provides the equivalent information.

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This commit is contained in:
Ross Thompson 2023-02-19 23:53:10 -06:00
parent 100e100835
commit 2d417c33a4
2 changed files with 9 additions and 23 deletions
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6
src/ifu/bpred/bpred.sv
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@ -69,7 +69,6 @@ module bpred (
output logic PredictionInstrClassWrongM // Class prediction is wrong output logic PredictionInstrClassWrongM // Class prediction is wrong
); );
logic PredValidF;
logic [1:0] DirPredictionF; logic [1:0] DirPredictionF;
logic [3:0] BTBPredInstrClassF, PredInstrClassF, PredInstrClassD; logic [3:0] BTBPredInstrClassF, PredInstrClassF, PredInstrClassD;
@ -148,7 +147,6 @@ module bpred (
.PCNextF, .PCF, .PCD, .PCE, .PCNextF, .PCF, .PCD, .PCE,
.PredPCF, .PredPCF,
.BTBPredInstrClassF, .BTBPredInstrClassF,
.PredValidF,
.AnyWrongPredInstrClassE, .AnyWrongPredInstrClassE,
.IEUAdrE, .IEUAdrE,
.InstrClassD, .InstrClassD,
@ -186,8 +184,8 @@ module bpred (
PredInstrClassF[1]; PredInstrClassF[1];
end else begin end else begin
assign PredInstrClassF = BTBPredInstrClassF; assign PredInstrClassF = BTBPredInstrClassF;
assign SelBPPredF = (PredInstrClassF[0] & DirPredictionF[1] & PredValidF) | assign SelBPPredF = (PredInstrClassF[0] & DirPredictionF[1]) |
PredInstrClassF[1] & PredValidF; PredInstrClassF[1];
end end
// Part 3 RAS // Part 3 RAS

26
src/ifu/bpred/btb.sv
View File

@ -37,7 +37,6 @@ module btb #(parameter int Depth = 10 ) (
input logic [`XLEN-1:0] PCNextF, PCF, PCD, PCE, // PC at various stages input logic [`XLEN-1:0] PCNextF, PCF, PCD, PCE, // PC at various stages
output logic [`XLEN-1:0] PredPCF, // BTB's guess at PC output logic [`XLEN-1:0] PredPCF, // BTB's guess at PC
output logic [3:0] BTBPredInstrClassF, // BTB's guess at instruction class output logic [3:0] BTBPredInstrClassF, // BTB's guess at instruction class
output logic PredValidF, // BTB's guess is valid
// update // update
input logic AnyWrongPredInstrClassE, // BTB's instruction class guess was wrong input logic AnyWrongPredInstrClassE, // BTB's instruction class guess was wrong
input logic [`XLEN-1:0] IEUAdrE, // Branch/jump target address to insert into btb input logic [`XLEN-1:0] IEUAdrE, // Branch/jump target address to insert into btb
@ -45,16 +44,13 @@ module btb #(parameter int Depth = 10 ) (
input logic [3:0] InstrClassE // Instruction class to insert into btb input logic [3:0] InstrClassE // Instruction class to insert into btb
); );
localparam TotalDepth = 2 ** Depth;
logic [TotalDepth-1:0] ValidBits;
logic [Depth-1:0] PCNextFIndex, PCFIndex, PCDIndex, PCEIndex; logic [Depth-1:0] PCNextFIndex, PCFIndex, PCDIndex, PCEIndex;
logic [`XLEN-1:0] ResetPC; logic [`XLEN-1:0] ResetPC;
logic MatchF, MatchD, MatchE, MatchNextX, MatchXF; logic MatchF, MatchD, MatchE, MatchNextX, MatchXF;
logic [`XLEN+4:0] ForwardBTBPrediction, ForwardBTBPredictionF; logic [`XLEN+3:0] ForwardBTBPrediction, ForwardBTBPredictionF;
logic [`XLEN+3:0] TableBTBPredictionF; logic [`XLEN+3:0] TableBTBPredictionF;
logic [`XLEN-1:0] PredPCD; logic [`XLEN-1:0] PredPCD;
logic UpdateEn; logic UpdateEn;
logic TablePredValidF, PredValidD;
// hashing function for indexing the PC // hashing function for indexing the PC
// We have Depth bits to index, but XLEN bits as the input. // We have Depth bits to index, but XLEN bits as the input.
@ -78,22 +74,14 @@ module btb #(parameter int Depth = 10 ) (
flopenr #(1) MatchReg(clk, reset, ~StallF, MatchNextX, MatchXF); flopenr #(1) MatchReg(clk, reset, ~StallF, MatchNextX, MatchXF);
assign ForwardBTBPrediction = MatchF ? {PredValidF, BTBPredInstrClassF, PredPCF} : assign ForwardBTBPrediction = MatchF ? {BTBPredInstrClassF, PredPCF} :
MatchD ? {PredValidD, InstrClassD, PredPCD} : MatchD ? {InstrClassD, PredPCD} :
{1'b1, InstrClassE, IEUAdrE} ; {InstrClassE, IEUAdrE} ;
flopenr #(`XLEN+5) ForwardBTBPredicitonReg(clk, reset, ~StallF, ForwardBTBPrediction, ForwardBTBPredictionF); flopenr #(`XLEN+4) ForwardBTBPredicitonReg(clk, reset, ~StallF, ForwardBTBPrediction, ForwardBTBPredictionF);
assign {PredValidF, BTBPredInstrClassF, PredPCF} = MatchXF ? ForwardBTBPredictionF : {TablePredValidF, TableBTBPredictionF}; assign {BTBPredInstrClassF, PredPCF} = MatchXF ? ForwardBTBPredictionF : {TableBTBPredictionF};
always_ff @ (posedge clk) begin
if (reset) begin
ValidBits <= #1 {TotalDepth{1'b0}};
end else if ((UpdateEn) & ~StallM & ~FlushM) begin
ValidBits[PCEIndex] <= #1 |InstrClassE;
end
if(~StallF | reset) TablePredValidF = ValidBits[PCNextFIndex];
end
assign UpdateEn = |InstrClassE | AnyWrongPredInstrClassE; assign UpdateEn = |InstrClassE | AnyWrongPredInstrClassE;
@ -102,6 +90,6 @@ module btb #(parameter int Depth = 10 ) (
.clk, .ce1(~StallF | reset), .ra1(PCNextFIndex), .rd1(TableBTBPredictionF), .clk, .ce1(~StallF | reset), .ra1(PCNextFIndex), .rd1(TableBTBPredictionF),
.ce2(~StallM & ~FlushM), .wa2(PCEIndex), .wd2({InstrClassE, IEUAdrE}), .we2(UpdateEn), .bwe2('1)); .ce2(~StallM & ~FlushM), .wa2(PCEIndex), .wd2({InstrClassE, IEUAdrE}), .we2(UpdateEn), .bwe2('1));
flopenrc #(`XLEN+1) BTBD(clk, reset, FlushD, ~StallD, {PredValidF, PredPCF}, {PredValidD, PredPCD}); flopenrc #(`XLEN) BTBD(clk, reset, FlushD, ~StallD, {PredPCF}, {PredPCD});
endmodule endmodule