Added synchronizer to reset

wally-pipelined/regression/lint-wally

@@ -7,7 +7,7 @@ verilator=`which verilator`
 basepath=$(dirname $0)/..
 for config in rv64g rv32g; do
     echo "$config linting..."
-    if !($verilator --lint-only --Wall  "$@" --top-module wallypipelinedsoc "-I$basepath/config/shared" "-I$basepath/config/$config" $basepath/src/*/*.sv $basepath/src/*/*/*.sv --relative-includes); then
+    if !($verilator --lint-only "$@" --top-module wallypipelinedsoc "-I$basepath/config/shared" "-I$basepath/config/$config" $basepath/src/*/*.sv $basepath/src/*/*/*.sv --relative-includes); then
         echo "Exiting after $config lint due to errors or warnings"
         exit 1
     fi
@@ -17,6 +17,5 @@ echo "All lints run with no errors or warnings"
 # --lint-only just runs lint rather than trying to compile and simulate
 # -I points to the include directory where files such as `include wally-config.vh  are found
 
-# For more exhaustive (and sometimes spurious) warnings, run:
-# verilator --lint-only -Wall -Iconfig/rv64ic src/*
+# For more exhaustive (and sometimes spurious) warnings, add --Wall to the Verilator command
 # Unfortunately, this produces a bunch of UNUSED and UNDRIVEN signal warnings in blocks that are configured to not exist.

wally-pipelined/src/wally/wallypipelinedsoc.sv

@@ -32,7 +32,8 @@
 `include "wally-config.vh"
 
 module wallypipelinedsoc (
-  input  logic             clk, reset, 
+  input  logic             clk, reset_ext, 
+  output logic             reset,
   // AHB Lite Interface
   // inputs from external memory
   input  logic [`AHBW-1:0] HRDATAEXT,
@@ -64,6 +65,9 @@ module wallypipelinedsoc (
   logic [3:0]       HSIZED;
   logic             HWRITED;
 
+  // synchronize reset to SOC clock domain
+  synchronizer resetsync(.clk, .d(reset_ext), .q(reset)); 
+   
   // instantiate processor and memories
   wallypipelinedhart hart(.clk, .reset,
     .TimerIntM, .ExtIntM, .SwIntM, 

wally-pipelined/testbench/testbench.sv

@@ -34,7 +34,7 @@ module testbench;
   parameter TEST="none";
  
   logic        clk;
-  logic        reset;
+  logic        reset_ext, reset;
 
   parameter SIGNATURESIZE = 5000000;
 
@@ -209,7 +209,7 @@ logic [3:0] dummy;
       ProgramAddrMapFile = {pathname, tests[test], ".elf.objdump.addr"};
       ProgramLabelMapFile = {pathname, tests[test], ".elf.objdump.lab"};
       $display("Read memfile %s", memfilename);
-      reset = 1; # 42; reset = 0;
+      reset_ext = 1; # 42; reset_ext = 0;
     end
 
   // generate clock to sequence tests
@@ -290,7 +290,7 @@ logic [3:0] dummy;
             ProgramAddrMapFile = {pathname, tests[test], ".elf.objdump.addr"};
             ProgramLabelMapFile = {pathname, tests[test], ".elf.objdump.lab"};
             $display("Read memfile %s", memfilename);
-            reset = 1; # 17; reset = 0;
+            reset_ext = 1; # 47; reset_ext = 0;
         end
       end
     end // always @ (negedge clk)