add LRSC test and add wally64a to regression

pipelined/regression/regression-wally

@@ -62,7 +62,7 @@ tc = TestCase(
       grepstr="400100000 instructions")
 #configs.append(tc) #temporarily removed until I make this checkpoint
 
-tests64gc = ["arch64i", "arch64priv", "arch64c",  "arch64m", "arch64d", "imperas64i", "imperas64f", "imperas64d", "imperas64m", "imperas64a",  "imperas64c", "wally64priv"] # , "imperas64mmu" "wally64i", #,  "testsBP64"] 
+tests64gc = ["arch64i", "arch64priv", "arch64c",  "arch64m", "arch64d", "imperas64i", "imperas64f", "imperas64d", "imperas64m", "wally64a",  "imperas64c", "wally64priv"] # , "imperas64mmu" "wally64i", #,  "testsBP64"] 
 for test in tests64gc:
   tc = TestCase(
         name=test,

pipelined/testbench/testbench.sv

@@ -91,7 +91,7 @@ logic [3:0] dummy;
         "imperas64f":   if (`F_SUPPORTED) tests = imperas64f;
         "imperas64d":   if (`D_SUPPORTED) tests = imperas64d;
         "imperas64m":   if (`M_SUPPORTED) tests = imperas64m;
-        "imperas64a":   if (`A_SUPPORTED) tests = imperas64a;
+        "wally64a":     if (`A_SUPPORTED) tests = wally64a;
         "imperas64c":   if (`C_SUPPORTED) tests = imperas64c;
                         else              tests = imperas64iNOc;
         "testsBP64":                      tests = testsBP64;

pipelined/testbench/tests.vh

@@ -44,10 +44,10 @@ string tvpaths[] = '{
     "coremark.bare.riscv", "100000"
   };
 
-  string imperas64a[] = '{
+  string wally64a[] = '{
-    `MYIMPERASTEST,
+    `WALLYTEST,
-    "rv64a/WALLY-AMO", "2110",
+    "rv64i_m/privilege/WALLY-AMO", "2210",
-    "rv64a/WALLY-LRSC", "2110"
+    "rv64i_m/privilege/WALLY-LRSC", "2410"
   };
 
     string imperas32a[] = '{

tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/Makefrag

@@ -38,6 +38,7 @@ rv64i_sc_tests = \
     WALLY-scratch-01 \
     WALLY-sscratch-s-01 \
     WALLY-AMO \
+    WALLY-LRSC \
 
 # Don't simulate these because they rely on SoC features that Wally does not offer.
 target_tests_nosim = \

tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-LRSC.reference_output

@@ -0,0 +1,24 @@
+fffffffe
+ffffffff
+00000000
+00000000
+0000002a
+00000000
+fffffffd
+ffffffff
+00000001
+00000000
+0000002a
+00000000
+fffffffb
+fffffff7
+00000000
+00000000
+0000002c
+00000000
+ffffffef
+ffffffdf
+00000001
+00000000
+0000002c
+00000000

tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-LRSC.S

@@ -0,0 +1,137 @@
+///////////////////////////////////////////
+// WALLY-LRSC.S
+//
+// Tests Atomic LR / SC instructions
+//
+// David_Harris@hmc.edu 7 March 2021
+//
+// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
+// Adapted from Imperas RISCV-TEST_SUITE
+//
+// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
+// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, 
+// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software 
+// is furnished to do so, subject to the following conditions:
+//
+// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
+//
+// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 
+// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 
+// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT 
+// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+///////////////////////////////////////////
+
+#include "model_test.h"
+#include "arch_test.h"
+
+RVTEST_ISA("RV64I")
+
+.section .text.init
+.globl rvtest_entry_point
+rvtest_entry_point:
+RVMODEL_BOOT
+
+    # ---------------------------------------------------------------------------------------------
+    # Addresses for test data and results
+    la x6, wally_signature
+    la  x31, test_data
+
+    # Testcase 0:  Do a successful load-reserved / store conditional word operation
+    li x11, 42  
+    lr.w x10, (x31)
+    sc.w x12, x11, (x31)
+    lw x13, 0(x31)
+    sd x10, 0(x6)       # should be fffffffffffffffe (sign extended value read from test data)
+    sd x12, 8(x6)       # should be 0000000000000000 (sc succeeded)
+    sd x13, 16(x6)      # should be 000000000000002A (value written by SC, in hex)
+
+ # Testcase 1:  Do an unsuccessful load-reserved / store conditional word operation
+	addi x6, x6, 24
+    addi x30, x31, 4
+    li x11, 43
+    lr.w x10, (x30)
+    sc.w x12, x11, (x31)  # should fail because not reserved
+    lw x13, 0(x31)
+    sd x10, 0(x6)       # should be fffffffffffffffd (sign extended value read from test data)
+    sd x12, 8(x6)       # should be 0000000000000001 (sc failed)
+    sd x13, 16(x6)      # should be 000000000000002A (previous value written by sc)
+
+    # Testcase 2:  Do a successful load-reserved / store conditional doubleword operation
+ 	addi x6, x6, 24
+    addi x31, x30, 4
+    li x11, 44
+    lr.d x10, (x31)
+    sc.d x12, x11, (x31)
+    lw x13, 0(x31)
+    sd x10, 0(x6)       # should be 0xfffffff7fffffffb (value read from test data)
+    sd x12, 8(x6)       # should be 0000000000000000 (sc succeeded)
+    sd x13, 16(x6)      # should be 000000000000002C (value written by SC)
+
+ # Testcase 3:  Do an unsuccessful load-reserved / store conditional doubleword operation
+	addi x6, x6, 24
+    addi x30, x31, 8
+    li x11, 45
+    lr.d x10, (x30)
+    sc.d x12, x11, (x31)  # should fail because not reserved
+    lw x13, 0(x31)
+    sd x10, 0(x6)       # should be 0xffffffdfffffffef (sign extended value read from test data)
+    sd x12, 8(x6)       # should be 0000000000000001 (sc failed)
+    sd x13, 16(x6)      # should be 000000000000002C (previous value written by sc)
+
+    # ---------------------------------------------------------------------------------------------
+RVMODEL_HALT
+
+RVTEST_DATA_BEGIN
+	.align 8
+test_data:
+
+	.dword 0xfffffffdfffffffe
+	.dword 0xfffffff7fffffffb
+	.dword 0xffffffdfffffffef
+	.dword 0xffffff7fffffffbf
+	.dword 0xfffffdfffffffeff
+	.dword 0xfffff7fffffffeff
+	.dword 0xffffdfffffffefff
+	.dword 0xffff7fffffffefff
+	.dword 0xfffdfffffffeffff
+	.dword 0xfff7fffffffbffff
+	.dword 0xffdfffffffefffff
+	.dword 0xff7fffffffbfffff
+	.dword 0xfdfffffffeffffff
+	.dword 0xf7fffffffeffffff
+	.dword 0xdfffffffefffffff
+	.dword 0x7fffffffefffffff
+	.dword 0x00000001ffffffff
+	.dword 0x0000000400000002
+	.dword 0x0000001000000008
+	.dword 0x0000004000000020
+	.dword 0x0000010000000080
+	.dword 0x0000040000000200
+	.dword 0x0000100000000800
+	.dword 0x0000400000002000
+	.dword 0x0000000100008000
+	.dword 0x0004000000000002
+	.dword 0x0000001000080000
+	.dword 0x0040000000000020
+	.dword 0x0000010000800000
+	.dword 0x0400000000000200
+	.dword 0x0000100008000000
+	.dword 0x4000000000002000
+	.dword 0x0000000080000000
+#ifdef rvtest_mtrap_routine
+mtrap_sigptr:
+    .fill 64*(XLEN/32),4,0xdeadbeef
+#endif
+
+#ifdef rvtest_gpr_save
+gpr_save:
+    .fill 32*(XLEN/32),4,0xdeadbeef
+#endif
+RVTEST_DATA_END
+
+RVMODEL_DATA_BEGIN
+# signature output
+wally_signature:
+.fill 12, 8, -1
+
+RVMODEL_DATA_END