forked from Github_Repos/cvw
RAS and RAS documentation now consistent.
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@ -42,7 +42,7 @@ module RASPredictor #(parameter int StackSize = 16 )(
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logic CounterEn;
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logic CounterEn;
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localparam Depth = $clog2(StackSize);
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localparam Depth = $clog2(StackSize);
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logic [Depth-1:0] NextPtr, Ptr, PtrP1, PtrM1;
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logic [Depth-1:0] NextPtr, Ptr, P1, M1, IncDecPtr;
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logic [StackSize-1:0] [`XLEN-1:0] memory;
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logic [StackSize-1:0] [`XLEN-1:0] memory;
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integer index;
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integer index;
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@ -71,10 +71,11 @@ module RASPredictor #(parameter int StackSize = 16 )(
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assign CounterEn = PopF | PushE | RepairD;
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assign CounterEn = PopF | PushE | RepairD;
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assign DecrementPtr = (PopF | DecRepairD) & ~IncrRepairD;
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assign DecrementPtr = (PopF | DecRepairD) & ~IncrRepairD;
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mux2 #(Depth) PtrMux(PtrP1, PtrM1, DecrementPtr, NextPtr);
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assign PtrM1 = Ptr - 1'b1;
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assign P1 = 1;
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assign PtrP1 = Ptr + 1'b1;
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assign M1 = '1; // -1
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mux2 #(Depth) PtrMux(P1, M1, DecrementPtr, IncDecPtr);
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assign NextPtr = Ptr + IncDecPtr;
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flopenr #(Depth) PTR(clk, reset, CounterEn, NextPtr, Ptr);
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flopenr #(Depth) PTR(clk, reset, CounterEn, NextPtr, Ptr);
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@ -84,7 +85,7 @@ module RASPredictor #(parameter int StackSize = 16 )(
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for(index=0; index<StackSize; index++)
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for(index=0; index<StackSize; index++)
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memory[index] <= {`XLEN{1'b0}};
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memory[index] <= {`XLEN{1'b0}};
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end else if(PushE) begin
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end else if(PushE) begin
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memory[PtrP1] <= #1 PCLinkE;
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memory[NextPtr] <= #1 PCLinkE;
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end
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end
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end
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end
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